Narrow active cell ie type trench gate igbt and a method for manufacturing a narrow active cell ie type trench gate igbt

ABSTRACT

In an equal width active cell IE type IGBT, a wide active cell IE type IGBT, and the like, an active cell region is equal in trench width to an inactive cell region, or the trench width of the inactive cell region is narrower. Accordingly, it is relatively easy to ensure the breakdown voltage. However, with such a structure, an attempt to enhance the IE effect entails problems such as further complication of the structure. The present invention provides a narrow active cell IE type IGBT having an active cell two-dimensional thinned-out structure, and not having a substrate trench for contact.

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure of Japanese Patent Application No. 2012-131915 filed onJun. 11, 2012 including the specification, drawings and abstract isincorporated herein by reference in its entirety.

BACKGROUND

The present invention relates to a semiconductor device (or asemiconductor integrated circuit device), and a method for manufacturinga semiconductor device (or a semiconductor integrated circuit device).More particularly, it relates to a technology effectively applicable toan IGBT device technology and a method for manufacturing an IGBT.

Japanese Unexamined Patent Publication No. Hei 11 (1999)-345969 (PatentDocument 1) relates to an equal-width active cell IE (Injection Enhance)type IGBT (Integrated Gate Bipolar Transistor) having equidistanttrenches. This document discloses therein a device structure in which anN+ type emitter region is finely divided along the longitudinaldirection by P+ body contact regions (so-called “active celltwo-dimensional thinned-out structure”).

Japanese Unexamined Patent Publication No. 2005-294649 (Patent Document2) relates to a wide active cell IE type IGBT in which the trenchinterval in an active cell region is larger than the trench interval inan inactive cell region. This document discloses therein a technology ofarranging a floating P type region extending to the trench bottom endson the opposite sides under the inactive cell region. Incidentally, inthis document, after trench formation, the floating P type region isintroduced simultaneously with the P type body region.

PATENT DOCUMENTS

-   [Patent Document 1] Japanese Unexamined Patent Publication No. Hei    11 (1999)-345969-   [Patent Document 2] Japanese Unexamined Patent Publication No.    2005-294649

SUMMARY

In an equal-width active cell IE type IGBT, a wide active cell IE typeIGBT, or the like, the trench widths in an active cell region and aninactive cell region are equal to each other, or the trench width in theinactive cell region is narrower. For this reason, it is possible toensure the breakdown voltage relatively easily. However, with such astructure, an attempt to enhance the IE effect unfavorably furthercomplicates the structure, and causes other problems.

Means and the like for solving such a problem will be described below.Other problems and novel features will be apparent from the descriptionof this specification and the accompanying drawings.

Summaries of the representative ones of the inventions disclosed in thepresent invention will be described in brief as follows.

Namely, the summary of one embodiment of the present invention is anarrow active cell IE type IGBT which has an active cell two-dimensionalthinned-out structure, and in which there is not arranged a body contactregion in a cross section orthogonal to the substrate surface, passingthrough the emitter region, and orthogonal to the trenches on theopposite sides.

The effects obtainable by representative ones of the embodimentsdisclosed in the present invention will be described in brief asfollows.

Namely, in accordance with one embodiment of the present invention, theIE effect can be enhanced while avoiding excessive complication of thedevice structure.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a top schematic layout view of a cell region and its peripheryof a narrow active cell IE type trench gate IGBT device chip forillustrating the outline of the device structure in a narrow active cellIE type trench gate IGBT of main embodiments (including modifiedexamples) of the present invention;

FIG. 2 is a device schematic cross-sectional view corresponding to anA-A′ cross section of a cell region end cut-out region R1 of FIG. 1;

FIG. 3 is a device schematic cross-sectional view corresponding to aB-B′ cross section of a cell region internal cut-out region R2 of FIG.1;

FIG. 4 is an enlarged top view of a linear unit cell region and itsperiphery R5 of FIG. 1 in accordance with one embodiment of the presentinvention;

FIG. 5 is an overall top view (roughly corresponding to FIG. 1, butclose to a more specific configuration) of the narrow active cell IEtype trench gate IGBT device chip of the one embodiment (also common toother embodiments and respective modified examples) of the presentinvention;

FIG. 6 is an enlarged top view of a portion corresponding to the cellregion internal cut-out region R3 of FIG. 5 for illustrating the devicestructure of the one embodiment (an active section dispersed structurein an active cell two-dimensional thinned-out structure) of the presentinvention;

FIG. 7 is a device cross-sectional view corresponding to a C-C′ crosssection of FIG. 6;

FIG. 8 is a device cross-sectional view corresponding to a D-D′ crosssection of FIG. 6;

FIG. 9 is a device cross-sectional view corresponding to an E-E′ crosssection of FIG. 6;

FIG. 10 is a device cross-sectional view in a manufacturing step (holebarrier region introduction step) corresponding to FIG. 7 forillustrating a manufacturing method corresponding to the devicestructure of the one embodiment of the present invention;

FIG. 11 is a device cross-sectional view in a manufacturing step (P typefloating region introduction step) corresponding to FIG. 7 forillustrating a manufacturing method corresponding to the devicestructure of the one embodiment of the present invention;

FIG. 12 is a device cross-sectional view in a manufacturing step (trenchprocessing hard mask deposition step) corresponding to FIG. 7 forillustrating a manufacturing method corresponding to the devicestructure of the one embodiment of the present invention;

FIG. 13 is a device cross-sectional view in a manufacturing step (trenchhard mask processing step) corresponding to FIG. 7 for illustrating amanufacturing method corresponding to the device structure of the oneembodiment of the present invention;

FIG. 14 is a device cross-sectional view in a manufacturing step (trenchprocessing step) corresponding to FIG. 7 for illustrating amanufacturing method corresponding to the device structure of the oneembodiment of the present invention;

FIG. 15 is a device cross-sectional view in a manufacturing step (trenchprocessing hard mask removing step) corresponding to FIG. 7 forillustrating a manufacturing method corresponding to the devicestructure of the one embodiment of the present invention;

FIG. 16 is a device cross-sectional view in a manufacturing step(drive-in diffusion and gate oxidation step) corresponding to FIG. 7 forillustrating a manufacturing method corresponding to the devicestructure of the one embodiment of the present invention;

FIG. 17 is a device cross-sectional view in a manufacturing step (gatepolysilicon etching back step) corresponding to FIG. 7 for illustratinga manufacturing method corresponding to the device structure of the oneembodiment of the present invention;

FIG. 18 is a device cross-sectional view in a manufacturing step (P typebody region and N+ type emitter region introduction step) correspondingto FIG. 7 for illustrating a manufacturing method corresponding to thedevice structure of the one embodiment of the present invention;

FIG. 19 is a device cross-sectional view in a manufacturing step (P+type body contact region and P+ type buried body contact regionintroduction step) corresponding to FIG. 8 for illustrating amanufacturing method corresponding to the device structure of the oneembodiment of the present invention;

FIG. 20 is a device cross-sectional view in a manufacturing step(interlayer insulation film deposition step) corresponding to FIG. 7 forillustrating a manufacturing method corresponding to the devicestructure of the one embodiment of the present invention;

FIG. 21 is a device cross-sectional view in a manufacturing step(contact hole formation step) corresponding to FIG. 7 for illustrating amanufacturing method corresponding to the device structure of the oneembodiment of the present invention;

FIG. 22 is a device cross-sectional view in a manufacturing step(surface metal deposition step) corresponding to FIG. 7 for illustratinga manufacturing method corresponding to the device structure of the oneembodiment of the present invention;

FIG. 23 is a device cross-sectional view in a manufacturing step (backsurface girding and back surface impurity introduction step)corresponding to FIG. 7 for illustrating a manufacturing methodcorresponding to the device structure of the one embodiment of thepresent invention;

FIG. 24 is a device cross-sectional view in a manufacturing step (backsurface metal electrode formation step) corresponding to FIG. 7 forillustrating a manufacturing method corresponding to the devicestructure of the one embodiment of the present invention;

FIG. 25 is a local detailed cross-sectional view of the device backsurface for a detailed description on the back surface side devicestructure of the narrow active cell IE type trench gate IGBT of the oneembodiment of the present invention, or for illustrating the devicestructure and the manufacturing method of a modified example(aluminum-doped structure);

FIG. 26 is an enlarged top view corresponding to FIG. 6, forillustrating Modified Example 1 (N+ type surface floating region & P+type surface floating region addition structure) regarding the surfaceside device structure of the narrow active cell IE type trench gate IGBTof the one embodiment of the present invention;

FIG. 27 is a device cross-sectional view corresponding to a F-F′ crosssection of FIG. 26;

FIG. 28 is a device cross-sectional view corresponding to a G-G′ crosssection of FIG. 26;

FIG. 29 is a device cross-sectional view corresponding to the C-C′ crosssection of FIG. 6 corresponding to FIG. 7 for illustrating ModifiedExample 2 (simplified active cell structure) regarding the surface sidedevice structure of the narrow active cell IE type trench gate IGBT ofthe one embodiment of the present invention;

FIG. 30 is a device schematic cross-sectional view of the A-A′ crosssection of the cell region end cut-out region R1 of FIG. 1 correspondingto FIG. 2 for illustrating Modified Example (hole collector celladdition structure) regarding the surface side device structure of thenarrow active cell IE type trench gate IGBT of the one embodiment of thepresent invention;

FIG. 31 is an enlarged top view of the linear unit cell region and itsperiphery R5 of FIG. 1 for illustrating Modified Example 3 (holecollector cell addition structure) regarding the surface side devicestructure of the narrow active cell IE type trench gate IGBT of the oneembodiment of the present invention;

FIG. 32 is an enlarged top view corresponding to FIG. 6 for illustratingModified Example 3 (hole collector cell addition structure) regardingthe surface side device structure of the narrow active cell IE typetrench gate IGBT of the one embodiment of the present invention;

FIG. 33 is a device cross-sectional view corresponding to a H-H′ crosssection of FIG. 32;

FIG. 34 is a device cross-sectional view corresponding to a J-J′ crosssection of FIG. 32;

FIG. 35 is a device cross-sectional view corresponding to a K-K′ crosssection of FIG. 32; and

FIG. 36 is an enlarged top view of the linear unit cell region and itsperiphery R5 of FIG. 1 for illustrating the outline of the devicestructure of the one embodiment of the present invention.

DETAILED DESCRIPTION Summary of Embodiments

First, a description will be given to the summary of representativeembodiments disclosed in the present invention.

1. A narrow active cell IE type trench gate IGBT includes:

(a) a silicon type semiconductor substrate having a first main surfaceand a second main surface;

(b) an IGBT cell region arranged on the first main surface side of thesilicon type semiconductor substrate;

(c) a plurality of linear active cell regions and a plurality of linearinactive cell regions arranged in the IGBT cell region;

(d) a plurality of active sections and a plurality of inactive sectionsalternately arrayed along the longitudinal direction of the each linearactive cell region;

(e) a trench arranged in the first main surface of the silicon typesemiconductor substrate, and at a boundary part between the each linearactive cell region and the each linear inactive cell region;

(f) a gate electrode arranged in the trench via an insulation film;

(g) an emitter region having a first conductivity type, arranged in asurface region on the first main surface side of the silicon typesemiconductor substrate, and over almost the entire region of the eachactive section;

(h) a body contact region having a second conductivity type, arranged inthe surface region on the first main surface side of the silicon typesemiconductor substrate, and in the each inactive section; and

(i) a metal emitter electrode arranged over the first main surface ofthe silicon type semiconductor substrate, and electrically coupled tothe emitter region and the body contact region.

2. In the narrow active cell IE type trench gate IGBT according to theitem 1, the body contact region is arranged over almost the entireregion of the each inactive section.

3. The narrow active cell IE type trench gate IGBT according to the item1 or 2, further includes:

(j) a second conductivity type floating region arranged in the surfaceregion on the first main surface side of the silicon type semiconductorsubstrate, and in almost the entire region of the each linear inactivecell region, in such a manner as to extend to the bottom ends of thetrenches on the opposite sides thereof.

4. The narrow active cell IE type trench gate IGBT according to any oneof the items 1 to 3, further includes:

(k) a hole barrier region having the first conductivity type, arrangedin the surface region on the first main surface side of the silicon typesemiconductor substrate, and in almost the entire region of the eachlinear active cell region, to the same level of depth as that of thebottom ends of the trenches on the opposite sides thereof.

5. The narrow active cell IE type trench gate IGBT according to any oneof the items 1 to 4, further includes:

(m) a buried body contact region having the second conductivity type,arranged in almost the entire surface of the layer underlying the bodycontact region in such a manner as to be in contact therewith.

6. In the narrow active cell IE type trench gate IGBT according to anyone of the items 1 to 5, the interval between the trenches on theopposite sides of the each linear active cell region is 0.35 micrometeror less.

7. In the narrow active cell IE type trench gate IGBT according to anyone of the items 1 to 6, the width in the longitudinal direction of theeach active section is 0.5 micrometer or less.

8. The narrow active cell IE type trench gate IGBT according to any oneof the items 1 to 7, further includes:

(n) a first conductivity type surface floating region arranged in thesurface region on the first main surface side of the silicon typesemiconductor substrate, and in the each linear inactive region at aposition on the extension of the emitter region in the adjacent linearactive region.

9. The narrow active cell IE type trench gate IGBT according to any oneof the items 1 to 8, further includes:

(p) a second conductivity type surface floating region arranged in thesurface region on the first main surface side of the silicon typesemiconductor substrate, and in the each linear inactive region at aposition on the extension of the body contact region in the adjacentlinear active region.

10. The narrow active cell IE type trench gate IGBT according to any oneof the items 1 to 9, further includes:

(q) a hole collector cell region arranged in such a manner as toalternately substitute for the linear active cell regions.

11. The narrow active cell IE type trench gate IGBT according to any oneof the items 1 to 10, further includes:

(r) a drift region having the first conductivity type, arranged from theinside to the first main surface in almost the entire region of thesilicon type semiconductor substrate;

(s) a field stop region arranged on the second main surface side of thedrift region in almost the entire region of the silicon typesemiconductor substrate, having the first conductivity type, and havinga higher concentration than that of the drift region;

(t) a collector region having the second conductivity type, arranged onthe second main surface side of the field stop region in almost theentire region of the silicon type semiconductor substrate;

(v) an aluminum doped region arranged on the second main surface side ofthe collector region in almost the entire region of the silicon typesemiconductor substrate, and having a higher concentration than that ofthe collector region; and

(w) a metal collector electrode arranged in almost the entire region ofthe second main surface of the silicon type semiconductor substrate.

Herein, a portion of the metal collector electrode in contact with thealuminum doped region is a back surface metal film including aluminum asa main component.

12. A method for manufacturing a narrow active cell IE type trench gateIGBT which includes:

(a) a silicon type semiconductor wafer having a first main surface and asecond main surface;

(b) an IGBT cell region arranged on the first main surface side of thesilicon type semiconductor wafer;

(c) a drift region having a first conductivity type, arranged from theinside to the first main surface in almost the entire region of thesilicon type semiconductor wafer;

(d) a body region having a second conductivity type, arranged in thesurface region on the first main surface side of the silicon typesemiconductor wafer, and in almost the entire surface of the IGBT cellregion;

(e) a plurality of linear active cell regions and a plurality of linearinactive cell regions arranged in the IGBT cell region;

(f) a plurality of active sections and a plurality of inactive sectionsalternately arrayed along the longitudinal direction of the each linearactive cell region;

(g) a trench arranged in the first main surface of the silicon typesemiconductor wafer, and at the boundary part between the each linearactive cell region and the each linear inactive cell region;

(h) a gate electrode arranged in the trench via an insulation film;

(i) an emitter region having the first conductivity type, arranged inthe surface region of the body region, and over almost the entire regionof the each active section;

(j) a body contact region having the second conductivity type, arrangedin the surface region of the body region, and in the each inactivesection;

(k) a second conductivity type floating region arranged in the surfaceregion on the first main surface side of the silicon type semiconductorwafer, and in almost the entire region of the each linear inactive cellregion, in such a manner as to extend to the bottom ends of the trencheson the opposite sides thereof, and having a larger depth than that ofthe body region; and

(m) a metal emitter electrode arranged over the first main surface ofthe silicon type semiconductor wafer, and electrically coupled to theemitter region and the body contact region.

The method includes the following steps:

(x1) introducing second conductivity type impurities for forming thesecond conductivity type floating region in the first main surface ofthe silicon type semiconductor wafer;

(x2) after the step (x1), forming the trench;

(x3) after the step (x2), carrying out drive-in diffusion with respectto the impurities introduced in the step (x1);

(x4) after the step (x3), forming the gate electrode; and

(x5) after the step (x4), introducing second conductivity typeimpurities for forming the body region.

13. The method for manufacturing a narrow active cell IE type trenchgate IGBT according to the item 12, further includes a step of:

(x6) before the step (x1), introducing first conductivity typeimpurities for forming a hole barrier region into the first main surfaceof the silicon type semiconductor wafer.

14. In the method for manufacturing a narrow active cell IE type trenchgate IGBT according to the item 12 or 13, the step (x1) is also used forintroducing second conductivity type impurities for forming a floatingfield ring arranged in the peripheral outside of the IGBT cell region.

15. The method for manufacturing a narrow active cell IE type trenchgate IGBT according to any one of the items 12 to 14, further includes astep of:

(x7) after the step (x5), introducing first conductivity type impuritiesfor forming the emitter region.

16. The method for manufacturing a narrow active cell IE type trenchgate IGBT according to the item 15, further includes a step of:

(x8) after the step (x7), introducing second conductivity typeimpurities for forming the body contact region.

[Explanation of Description Form, Basic Terms, and Methods in thePresent Invention]

1. In the present invention, the embodiment may be described in aplurality of divided sections for convenience, if required. However,unless otherwise specified, these are not independent of each other, butare respective portions of a single example, or are in a relation suchthat one is details of a part, a modified example, or the like of a partor the whole of the other. Further, in principle, description on thesimilar portions is not repeated. Furthermore, respective structuralelements in embodiments are not essential, unless otherwise specified,and except when they are theoretically limited to the numbers, andunless otherwise apparent from the context.

Further, the term “semiconductor device” used in the present inventionembraces, mainly, various transistors (active elements) alone, or theone obtained by integrating resistors, capacitors, and the like aroundthem as the center over a semiconductor chip or the like (for example,single crystal silicon substrate), and the one obtained by packagingsemiconductor chips and the like. Herein, representative examples of thevarious transistors may include MOSFETs (Metal Insulator SemiconductorField Effect Transistors) typified by MOSFETs (Metal Oxide SemiconductorField Effect Transistors). Then, representative examples of the varioussingle transistors may include power MOSFETs and IGBTs (Insulated GateBipolar Transistors). These are generally classified into powersemiconductor devices, which include therein, other than power MOSFETsand IGBTs, bipolar power transistors, thyristors, power diodes, and thelike.

Representative form of the power MOSFET is a double diffused verticalpower MOSFET including a source electrode at the front surface, and adrain electrode at the back surface. The double diffused vertical powerMOSFETs can be mainly classified into two kinds. The first is a planargate type mainly described in embodiments, and the second is a trenchgate type such as U-MOSFET.

The power MOSFETs includes, other than these, LD-MOSFETs(lateral-diffused MOSFETs).

2. Similarly, in the description of embodiments, and the like, even theterm “X including A” or the like for the material, composition, or thelike does not exclude the one including an element other than A as amain structural element unless otherwise specified and unless otherwiseapparent from the context. For example, for the component, the term isused to embrace “X including A as a main component”, and the like. Forexample, it is naturally understood that even the term “silicon member”or the like herein used is not limited to pure silicon but also embracesa SiGe alloy, other multinary alloys containing silicon as a maincomponent, and other members containing additives, and the like.

Similarly, the terms “silicon oxide film”, “silicon oxide typeinsulation film”, and the like are used to embrace insulation filmsincluding not only relatively pure undoped silicon dioxide, but alsoother silicon oxides as main components. For example, impurity-dopedsilicon oxide type insulation films such as TEOS-based silicon oxide,PSG (phosphorus silicate glass), and BPSG (borophosphosilicate glass)are also silicon oxide films. Whereas, other than thermal oxide filmsand CVD oxide films, coating type films such as SOG (Spin On Glass) andNSC (nano-clustering silica) are also silicon oxide films or siliconoxide type insulation films. Other than these, a low-k insulation filmsuch as FSG (fluorosilicate glass), SiOC (Silicon Oxicarbide),carbon-doped silicon oxide, or OSG (organosilicate glass) is alsosimilarly a silicon oxide film or a silicon oxide type insulation film.Further, the silica type low-k insulation films obtained by introducingholes into the same members as these (porous type insulation films, the“porous” herein used also embraces molecular porous) are also siliconoxide films or silicon oxide type insulation films

Further, silicon type insulation films which are commonly used alongwith silicon oxide type insulator films in the field of semiconductorsinclude silicon nitride type insulation films. Materials belonging tosuch a group include SiN, SiCN, SiNH, SiCNH, or the like. The term“silicon nitride” herein used embraces both SiN and SiNH unlessotherwise specified. Similarly, the term “SiCN” herein used embracesboth SiCN and SiCNH unless otherwise specified.

3. Similarly, although preferred examples are shown with respect toconfiguration, position, attribute, and the like, it is naturallyunderstood that the present invention is not strictly limited theretounless otherwise specified and unless otherwise apparent from thecontext.

4. Further, also when specific numerical values and quantities arementioned, unless otherwise specified, except when they aretheoretically limited to the numbers, and unless otherwise apparent fromthe context, each numerical value may be a numerical value of more thanthe specific numerical value, or may be a numerical value of less thanthe specific numerical value.

5. The term “wafer” herein used generally refers to a single crystalsilicon wafer over which a semiconductor device (which may be asemiconductor integrated circuit device or an electronic device) is tobe formed. However, it is naturally understood that the term alsoembraces a composite wafer of insulation substrate such as an epitaxialwafer, a SOI substrate, or a LCD glass substrate, and a semiconductorlayer or the like.

6. Similarly to the previous description on the power MOSFETs, ingeneral, IGBTs are largely classified into a planar gate type and atrench gate type. The trench gate type IGBT has a relatively lower ONresistance. However, in order to further promote the conductivitymodulation, and to further reduce the ON resistance, there has beendeveloped “an IE type trench gate IGBT” (or “active cell thinned-outtype trench gate IGBT”) utilizing the IE (Injection Enhancement) effect.The IE type trench gate IGBT has the following structure: in the cellregion, active cells actually coupled to an emitter electrode, andinactive cells having P type floating regions are arranged alternately,or in the form of the teeth of a comb, thereby to facilitate theaccumulation of holes on the device main surface side (emitter side) ofa semiconductor substrate. Incidentally, the P type floating region isnot essential. However, the presence of a P type floating region (i.e.,a P type deep floating region) having a depth enough to cover the lowerends of the trenches on the opposite sides provides a merit offacilitating breakdown voltage design.

Incidentally, in the present invention, there are a plurality of activecells. The first is an intrinsic active cell which actually has an N+emitter region, and in which a trench gate electrode is electricallycoupled to a metal gate electrode (specifically, a linear active cellregion). The second is a pseud active cell which does not have an N+emitter region, and in which a trench gate electrode is electricallycoupled to a metal emitter electrode (specifically, a linear holecollector cell region).

7. In the present invention, of the IE type trench gate IGBTs, the onein which the width of the main active cell is narrower than the width ofthe main inactive cell is referred to as a “narrow active cell IE typetrench gate IGBT”. More generally, the term refers to the one in whichthe pitch between the trenches (the distance between the trench centers)of the active cell is narrower than the pitch between trenches of theinactive cell.

Further, the direction crossing the trench gate is referred to as a“width direction of the cell” and the direction of extension(longitudinal direction) of the trench gate (linear gate portion)orthogonal thereto is referred to as a “length direction of the cell”.

The present invention mainly deals with the “linear unit cell region”(including, for example, the linear active cell region and the linearinactive cell region). The linear unit cell regions are arrayed in aperiodically repeating manner in the inside region of the semiconductorchip, to form a “cell formation region”, i.e., an “IGBT cell region”.

Around the cell region, generally, there is arranged a cell peripheraljunction region. Further, therearound, a floating field ring or a fieldlimiting ring, and the like are arranged, thereby to form a terminationstructure. Herein, the term “floating field ring” or “field limitingring” refers to the following. Namely, the term refers to an impurityregion or an impurity region group arranged apart from a P type bodyregion (P type well region) in the front surface (device surface) of thedrift region, having the same conductivity type as that, and the similarconcentration to that (which is a concentration enough to prevent fulldepletion when the main junction is applied with a reverse voltage), andsurrounding the cell region in one-fold or multi-fold (e.g., about10-fold) rings.

Further, in the floating field rings, there may be arranged a fieldplate. The field plate is a conductor film pattern coupled to thefloating field ring, and refers to a portion which extends over thefront surface (device surface) of the drift region via an insulationfilm, and surrounds the cell region in a ring.

The linear unit cell region as a periodical element forming the cellregion refers to the following, for example, in the example of FIG. 5.Namely, the one in which half-width linear inactive cell regions arearranged on the opposite sides of the linear active cell region as thecenter is rationally treated as a set. However, specifically, when thelinear inactive cell regions are individually described, they areinconveniently separated to opposite sides. For this reason, in thatcase, a specific integral portion is referred to as a linear inactivecell region.

Incidentally in the following example, a “contact substrate trench”commonly used for implementing an “ultra-narrow active region” is notformed, but a contact trench is formed in the interlayer insulation filmover a flat substrate surface. Herein, in the present invention, theterm “ultra-narrow active region” refers to the one having a distancebetween the inner sides of the trenches on the opposite sides of theactive cell region, namely, a width of the active region betweentrenches of 0.35 micrometer or less. Whereas, the one having a width inthe longitudinal direction of the active section (referred to as an“active section width”) of 0.5 micrometer or less is referred to as an“ultra-narrow active section”.

Details of Embodiments

Embodiments will be further described in details. In respectivedrawings, the same or similar portions are indicated with the same orsimilar reference signs and reference numerals, and a descriptionthereon will not be repeated in principle.

Further, in the accompanying drawings, hatching or the like may beomitted even in cross section when it rather complicates the drawing, orwhen it is apparently distinct from the gap. In conjunction with this,when apparent from the description or the like, or in other cases, evenfor a two-dimensionally closed hole, the background outline may beomitted. Further, even not in cross section, hatching may be added inorder to clearly demonstrate that the part is not a gap.

Incidentally, regarding the designation in the alternative case, whenone is referred to as “first”, and the other is referred to as “second”,or the like, they may be exemplified correspondingly in accordance withrepresentative embodiments. However, it is naturally understood that,for example, even the term “first” is not limited to the exemplifiedalternatives.

Incidentally, as the prior patent applications disclosing an IE typeIGBT having different-interval trenches, there are, for example,Japanese Patent Application No. 2012-19942 (filing date in Japan, Feb.1, 2012), Japanese Patent Application No. 2012-577 (filing date inJapan, Jan. 5, 2012), and Japanese Patent Application No. 2011-127305(filing date in Japan, Jun. 7, 2011).

1. Explanation of Outline of Device Structure in Narrow Active Cell IEType Trench Gate IGBT in Main Embodiment (Including Modified Example) ofthe Present Invention (Mainly FIGS. 1 to 4)

In this section, specific examples are shown, thereby to complement theprevious definitions, and representative specific examples of thepresent invention are drawn, and the outline thereof is illustrated. Inaddition, the overall preliminary description is given. Incidentally, inFIGS. 2 and 3, in order to ensure the simplicity of the wide area view,the structure of some impurity region is shown in a largely simplifiedform (for the detailed structure, see, e.g., FIG. 4).

FIG. 1 is a top schematic layout view of a cell region and its peripheryof a narrow active cell IE type trench gate IGBT device chip forillustrating the outline of the device structure in a narrow active cellIE type trench gate IGBT of main embodiments (including modifiedexamples) of the present invention. FIG. 2 is a device schematiccross-sectional view corresponding to an A-A′ cross section of a cellregion end cut-out region R1 of FIG. 1. FIG. 3 is a device schematiccross-sectional view corresponding to a B-B′ cross section of a cellregion internal cut-out region R2 of FIG. 1. FIG. 4 is an enlarged topview of a linear unit cell region and its periphery R5 of FIG. 1 inaccordance with one embodiment of the present invention. Based on these,a description will be given to the outline of the device structure inthe narrow active cell IE type trench gate IGBT in the main embodiment(including a modified example).

(1) Explanation of Cell Region and its Peripheral Planar Structure(Mainly FIG. 1):

First, FIG. 1 shows the top view of the inside region (the portioninside a guard ring or the like which is the outermost part of thetermination structure, i.e., the main part of a chip 2) of the IE typetrench gate IGBT which is the main object of the present invention. Asshown in FIG. 1, the main part of the internal region of the chip 2(semiconductor substrate) is occupied by an IGBT cell region 10. In theouter circumferential part of the cell region 10, a ring-shaped and Ptype cell peripheral junction region 35 is arranged in such a manner asto surround this. Outside the cell peripheral junction region 35, asingle or a plurality of ring-shaped and P type floating field rings 36(i.e., field limiting rings) are arranged at an interval, and form atermination structure for the cell region 10 together with the cellperipheral junction region 35, a guard ring 4 (see FIG. 5), and thelike.

In the cell region 10, in this example, a large number of linear unitcell regions 40 are spread. In the end regions thereof, there arearranged a pair of or more (for one side, one row or about several rows)of dummy cell regions 34 (linear dummy cell regions).

(2) Explanation of Narrow Active Cell Type Unit Cell and Alternate ArraySystem (Mainly FIG. 2):

Then, FIG. 2 shows the A-A′ cross section of the cell region end cut-outregion R1 of FIG. 1. As shown in FIG. 2, in the semiconductor region (inthis example, silicon single crystal region) of the back surface 1 b(the back side main surface or the second main surface of thesemiconductor substrate) of the chip 2, there is arranged a P+ typecollector region 18. Over the surface, there is arranged a metalcollector electrode 17. Between an N− type drift region 20 (firstconductivity type drift region) forming the main part of thesemiconductor substrate 2 and the P+ type collector region 18 (secondconductivity type collector region), there is arranged an N type fieldstop region 19 (first conductivity type field stop region).

On the other hand, in the semiconductor region on the front surface side1 a (the front side main surface or the first main surface of thesemiconductor substrate) of the N− type drift region 20, there arearranged a large number of trenches 21. Therein, trench gate electrodes14 are embedded via a gate insulation film 22, respectively. The trenchgate electrodes 14 are coupled via a metal gate wire 7 to a metal gateelectrode 5 (see FIG. 5).

Further, the trenches 21 perform a function of defining respectiveregions. For example, a dummy cell region 34 is defined from oppositesides thereof by a pair of trenches 21. One trench 21 of these definesthe cell region 10 and the cell peripheral junction region 35. The cellperipheral junction region 35 is coupled via a P+ type body contactregion 25 p to a metal emitter electrode 8. Incidentally, in the presentinvention, unless otherwise specified, the thickness of the gateinsulation film 22 at any portion of the trench is assumed to be roughlyequal (however, it is not excluded that, if required, a given portion isdifferent in thickness from other portions). Thus, in the cellperipheral junction region 35 and the dummy cell region 34, an emittercontact is established. As a result, even when the width of the dummycell region 34 or the like is changed in layout, it is possible toprevent the reduction of the breakdown voltage. Namely, the degree offreedom for design is improved.

In the semiconductor region on the front surface side 1 a of the N− typedrift region 20 outside the cell peripheral junction region 35, there isarranged a P type floating field ring 36. Over the front surface 1 a, afield plate 4 is arranged, and is coupled via a P+ type body contactregion 25 r to the floating field ring 36.

Then, the cell region 10 will be further described. The dummy cellregion 34 is basically equal in both structure and size to the linearactive cell region 40 a except for not having an N+ type emitter region12. A P+ type body contact region 25 d arranged in the front surface ofthe P type body region 15 is coupled to the metal emitter electrode 8.

Most of the inside region of the cell region 10 basically has arepeating structure of translational symmetry with the linear unit cellregion 40 as a unit cell (incidentally, symmetry in a strict sense isnot required. The same shall apply hereinafter). The linear unit cellregion 40 as the unit cell includes the linear active cell region 40 a,and half-width linear inactive cell regions 40 i on the opposite sidesthereof. However, specifically, it can be seen that full-width linearinactive cell region 40 i is arranged between the adjacent linear activecell regions 40 a (see FIG. 4).

In the semiconductor surface region on the front side main surface 1 a(first main surface) side of the semiconductor substrate of the linearactive cell region 40 a, there is arranged the P type body region 15. Inthe front surface thereof, there are arranged an N+ type emitter region12 (first conductivity type emitter region) and a P+ type body contactregion 25. The N+ type emitter region 12 and the P+ type body contactregion 25 are coupled to the metal emitter electrode 8. In the linearactive cell region 40 a, in the N− type drift region 20 under the P typebody region 15, there is arranged an N type hole barrier region 24. Ineach example of the present invention, when the N type hole barrierregion 24 is arranged, in principle, from the two-dimensional viewpoint,it is arranged in almost the entire region of the linear active cellregion 40 a. Incidentally, it is naturally understood that this is notessential, and can also be partially arranged, if required.

On the other hand, in the front side main surface 1 a (first mainsurface) side semiconductor surface region of the semiconductorsubstrate in the linear inactive cell region 40 i, similarly, the P typebody region 15 is arranged. In the underlying N− type drift region 20,there is arranged a P type floating region 16 (second conductivity typefloating region) covering the lower ends of the trenches 21 on theopposite sides, and deeper than them. By arranging such a P typefloating region 16, it is possible to widen the width Wi of the linearinactive cell region without causing a sharp reduction of the breakdownvoltage. For example, even when the layout is adjusted in order tooptimize the characteristics such as the gate capacity, ON voltage, andswitching characteristics, there is no fear of the reduction of thebreakdown voltage, and the degree of freedom for design can be ensured.Further, for example, when the concentration of the N type hole barrierregion 24 is increased for optimization, similarly, there is almost noeffect on the breakdown voltage. As a result of this, it becomespossible to effectively enhance or control the hole accumulation effect.Incidentally, in the IE type trench gate IGBT, there is not formed acontact from the emitter electrode 8 to the P type floating region 16.This is as follows: the direct hole discharge path from the P typefloating region 16 to the emitter electrode 8 is blocked, which resultsin an increase in hole concentration of the N− type drift region 20 (Nbase region) under the linear active cell region 40 a; as a result, theelectron concentration to be injected from the MOSFET into the N baseregion in the IGBT is improved, thereby to reduce the ON resistance.

In this example, the width Wa of the linear active cell region 40 a isset narrower than the width Wi of the linear inactive cell region 40 i.In the present invention, this is referred to as a “narrow active celltype unit cell”. Below, mainly, a device having the narrow active celltype unit cell will be specifically described. However, the presentinvention is not limited thereto. It is naturally understood that thepresent invention is also applicable to a device having a “non-narrowactive cell type unit cell”.

In the example of FIG. 2, the linear active cell regions 40 a and thelinear inactive cell regions 40 i are alternately arrayed to form thelinear unit cell region 40. This configuration is referred to as an“alternate array system” in the present invention. Below, unlessotherwise specified (specifically, basically other than FIG. 3), adescription will be given on the premise of the alternate array system.However, it is naturally understood that the “non-alternate arraysystem” is also acceptable.

In FIG. 2, a description was given to the main part exemplarilyincluding respective portions of various embodiments of the presentinvention. However, in the following description, these are divided intostructural elements such as a cell part (cross-sectional or planarstructure), and a cell peripheral part to be described. However, theseare not individually independent of one another. As shown in FIG. 2,various modified examples substitute for respective structural elementsto form the main part. This is not limited to FIG. 2, and can also applyto the subsequent FIG. 3.

In FIG. 2 (alternate array system), the one obtained by substitutingevery other active cell with a hole collector cell is the structureshown in FIG. 30 or the like. However, it is naturally understood thatthe same substitution can also be carried out in the non-alternate arraysystem as in FIG. 3.

(3) Explanation of Non-Alternate Array System (Mainly FIG. 3):

Then, FIG. 3 shows a specific example of the linear unit cell region 40of the non-alternate array system. As shown in FIG. 3, in the example ofFIG. 2, the number of the linear inactive cell regions 401 to beinserted in between the adjacent linear active cell regions 40 a is one.However, in the example of FIG. 3, the number of the linear inactivesub-cell regions 40 is (device element corresponding to the linearinactive cell region 40 i of FIG. 2) to be inserted in between theadjacent linear active cell regions 40 a is plural. Also in the exampleof the non-alternate array system, mainly, the width Wa of the linearactive cell region 40 a is set narrower than the width Wis of the linearinactive sub-cell region 40 is. As with the foregoing, in the presentinvention, this is referred to as a “narrow active cell type unit cell”.Namely, the definition of the narrow active cell type unit cell is donenot by the width Wi of the linear inactive cell region 40 i but by thewidth Wis of the linear inactive sub-cell region 40 is. Incidentally,the number (which will be hereinafter referred to as an “insertionnumber”) of the linear inactive sub-cell regions 40 is to be inserted inbetween the adjacent linear active cell regions 40 a is not required tobe constant, but may be changed between one and several according to theplace.

Similarly to this, also in the alternate array system, in some cases,the insertion number may be set plural. Incidentally, the merit of thealternate array system is as follows: the number of trenches is small,and hence the planar structure can be relatively simplified. Further,there is also a merit of preventing an inadvertent increase in gatecapacity. On the other hand, the merit of the non-alternate array systemresides in that the width Wi of the relatively wider linear inactivecell region can be set without making the gate capacity too small, andwithout reducing the breakdown voltage. The overall design optimizationmay become difficult with a too small gate capacity according to theapplication or the gate drive conditions. For this reason, it iseffective to ensure the adjustable means as device design, if required.

(4) Explanation of Active Cell Two-Dimensional Thinned-Out Structure(Mainly FIG. 4)

FIG. 4 shows one example of the detailed planar structure of the linearunit cell region main part and its peripheral cut-out region R5 ofFIG. 1. As shown in FIG. 4, in the length direction of the linear activecell region 40 a, for example, active sections 40 aa having a givenlength are arranged at a given interval, between which there is aninactive section 40 ai not including the N+ type emitter region 12arranged therein. Namely, some portions in the length direction of thelinear active cell region 40 a locally and dispersively become theactive sections 40 aa. A further description will be given. In theactive section 40 aa, in almost the entire surface thereof, there isarranged the N+ type emitter region 12. In the inactive section 40 ai,in almost the entire surface thereof, there are arranged a P+ type bodycontact region 25 and a P+ type buried body contact region 55. On theother hand, in the linear inactive cell region 40 i, in almost theentire surface thereof, there are arranged the P type body region 15 andthe P type floating region 16 (second conductivity type floatingregion).

Incidentally, herein, “being distributed with a given length at a giveninterval” means “being periodical”. However, “being substantiallyperiodical” corresponds to the local and dispersive distribution.However, “being local and dispersive” is “being wider than that” anddoes not necessarily mean “being periodical or quasi-periodical”.

2. Explanation of Device Structure of Narrow Active Cell IE Type TrenchGate IGBT in One Embodiment of the Present Invention (P Type DeepFloating & Hole Barrier Combination Structure) (Mainly FIGS. 5 to 9)

In this section, based on the explanation of Section 1, a descriptionwill be given to one example of the specific chip top surface layout andthe unit cell structure (active cell one-dimensional thinned-outstructure) common to respective embodiments (corresponding to FIGS. 1,2, and 4 of Section 1). The cell structure described in this section isa narrow active cell type unit cell of the alternate array system.

Incidentally, generally, with an IGBT element 2 with a breakdown voltageof 1200 volts as an example, the chip size is 3 to 15 millimeterssquare. Thus, the chip size largely varies according to the assumedcurrent value. Herein, for convenience of description, a descriptionwill be given by taking a chip 4 millimeters long, and 5.2 millimeterswide as an example. Herein, a description will be given by assuming thebreakdown voltage of the device as, for example, about 1200 volts.

FIG. 5 is an overall top view (roughly corresponding to FIG. 1, butclose to a more specific configuration) of the narrow active cell IEtype trench gate IGBT device chip of the one embodiment (also common toother embodiments and respective modified examples) of the presentinvention. FIG. 6 is an enlarged top view of a portion corresponding tothe cell region internal cut-out region R3 of FIG. 5 for illustratingthe device structure of the one embodiment (an active section dispersedstructure in an active cell two-dimensional thinned-out structure) ofthe present invention. FIG. 7 is a device cross-sectional viewcorresponding to a C-C′ cross section of FIG. 6. FIG. 8 is a devicecross-sectional view corresponding to a D-D′ cross section of FIG. 6.FIG. 9 is a device cross-sectional view corresponding to an E-E′ crosssection of FIG. 6. Based on these, a description will be given to thedevice structure of the narrow active cell IE type trench gate IGBT inone embodiment (P type deep floating & hole barrier combinationstructure) of the present invention.

As shown in FIG. 5, in the outer circumferential part of the top surface1 a of the IGBT device chip 2, there is arranged a ring-shaped guardring 3 formed of, for example, an aluminum type wiring layer. In theinside thereof, there are arranged several (single or plural)ring-shaped field plates 4 (formed of, for example, the same aluminumtype wiring layer as the previous one) coupled to a ring-shaped floatingfield ring or the like. Inside the field plate 4 (floating field ring36), and in the main part of the inside region of the top surface 1 a ofthe chip 2, there is arranged the cell region 10. The top of the cellregion 10 is covered to the vicinity of the outside thereof with a metalemitter electrode 8 formed of, for example, the same aluminum typewiring layer as the previous one. The central part of the metal emitterelectrode 8 becomes a metal emitter pad 9 to be coupled with a bondingwire or the like. Between the metal emitter electrode 8 and the fieldplate 4, there is arranged a metal gate wire 7 formed of, for example,the same aluminum type wiring layer as the previous one. The metal gatewire 7 is coupled to the metal gate electrode 5 formed of, for example,the same aluminum type wiring layer as the previous one. The centralpart of the metal gate electrode 5 becomes a gate pad 6 to be coupledwith a bonding wire or the like.

Then, FIG. 6 shows an enlarged planar layout of the cell region internalcut-out region R3 of FIG. 5 (mainly showing the layout of the surfaceregion of the semiconductor substrate). As shown in FIG. 6, the N+ typeemitter region 12 is not formed over almost the full length of thelinear active cell region 40 a. The linear active cell region 40 a isalmost periodically divided in the length direction thereof into activesections 40 aa each including the N+ type emitter region 12 formedtherein, and inactive sections 40 ai each not including the N+ typeemitter region 12 formed therein. Namely, the N+ type emitter region 12is arranged over almost the entire surface in the active section 40 aaof the linear active cell region 40 a. The P+ type body contact region25 is arranged over almost the entire surface in the inactive section 40ai of the linear active cell region 40 a. On the other hand, in thelinear inactive cell regions 40 i separated by the linear active cellregions 40 a and the trench gate electrodes 14, the P type body region15 and the P type floating region 16 are arranged over almost the entiresurface thereof.

Then, FIG. 7 shows the C-C′ cross section of FIG. 6. As shown in FIG. 7,in the semiconductor region of the back surface 1 b of the semiconductorchip 2, a P+ type collector region 18 and an N type field stop region 19are formed in such a manner as to be vertically in contact with eachother. Over the back surface 1 b of the semiconductor chip 2, there isformed a metal collector electrode 17.

In the N− type drift region 20 (the semiconductor region on the frontsurface side of the semiconductor substrate) on the front surface 1 a(first main surface) side of the semiconductor chip 2 in the linearactive cell region 40 a, there are arranged an N type hole barrierregion 24, a P type body region 15, and an N+ type emitter region 12sequentially from the bottom. Further, over the front surface 1 a of thesemiconductor chip 2, there is formed an interlayer insulation film 26.In the interlayer insulation film 26 portion in the linear active cellregion 40 a, there is formed a contact trench 11 (or contact hole). TheN+ type emitter region 12 is coupled via the contact trench 11 and thelike to the metal emitter electrode 8 arranged over the interlayerinsulation film 26. The presence of the N type hole barrier region 24 isarbitrary. However, the N type hole barrier region 24 is present, andthereby acts as a hole barrier. In addition, the presence thereof has aneffect of preventing the P type floating region 16 from undesirablyexpanding toward the linear active cell region 40 a side even when thewidth of the linear active cell region 40 a becomes very narrow.Further, the disposition of the N type hole barrier region 24 has amerit capable of implementing a sufficient IE effect even when the depthof the trench is not very large (e.g., about 3 micrometers). Further,there is also an effect capable of largely reducing the range ofcharacteristic fluctuation with respect to the variation in trenchdepth.

Herein, the N type hole barrier region 24 is a barrier region forinhibiting holes from flowing into the path from the N− type driftregion 20 to the N+ type emitter region 12. The impurity concentrationthereof is, for example, lower than that of the N+ type emitter region12, and higher than that of the N− type drift region 20. The presence ofthe N type hole barrier region 24 can effectively inhibit the holesaccumulated in the linear inactive cell region 40 i from entering intothe emitter path (the path from the N− type drift region 20 toward theP+ type body contact region 25) in the linear active cell region 40 a.Further, the N type hole barrier region 24 is locally arranged only inthe active cell region 40 a. This prevents an unnecessary increase indischarge resistance of holes at the time of switching-off, whichprevents degradation of the switching characteristics.

In contrast to this, in the N− type drift region 20 on the front surface1 a (first main surface) side of the semiconductor chip 2 in the linearinactive cell region 40 i (the surface-side semiconductor region of thesemiconductor substrate), a P type floating region 16 and a P type bodyregion 15 are arranged sequentially from the bottom. The depth of the Ptype floating region 16 is set larger than the depth of the trench 21,and is distributed in such a manner as to cover the lower end of thetrench 21. In this manner, it is possible to effectively prevent theconcentration of the electric field intensity to the lower end of thetrench 21 in the off state.

Then, FIG. 8 shows the D-D′ cross section of FIG. 6. As shown in FIG. 8,this cross section is different from FIG. 7 in that the P+ type bodycontact region 25 is arranged over the front surface of the P type bodyregion 15 in the linear active cell region 40 a, and in that a P+ typeburied body contact region 55 is arranged in contact with the bottom ina superposed manner. Incidentally, other portions are entirely the sameas in FIG. 7.

Then, FIG. 9 shows the E-E′ cross section of FIG. 6. As shown in FIG. 9,in the semiconductor region of the back surface 1 b of the semiconductorchip 2, a P+ type collector region 18 and an N type field stop region 19are formed in such a manner as to be vertically in contact with eachother. Over the back surface 1 b of the semiconductor chip 2, there isformed a metal collector electrode 17.

In the N− type drift region 20 on the front surface 1 a (first mainsurface) side of the semiconductor chip 2 in the active section 40 aa ofthe linear active cell region 40 a (in the front surface sidesemiconductor region of the semiconductor substrate), the N type holebarrier region 24, the P type body region 15, and the N+ type emitterregion 12 are arranged sequentially from the bottom. On the other hand,in the N− type drift region 20 on the front surface 1 a (first mainsurface) side of the semiconductor chip 2 in the inactive section 40 aiof the linear active cell region 40 a (the front surface sidesemiconductor region of the semiconductor substrate), the N type holebarrier region 24, the P type body region 15, the P+ type buried bodycontact region 55, and the P+ type body contact region 25 are arrangedsequentially from the bottom. Similarly to above, over the front surface1 a of the semiconductor chip 2, there is formed the contact trench 11(or a contact hole). The N+ type emitter region 12 and the P+ type bodycontact region 25 are coupled via the contact trench 11 and the like tothe metal emitter electrode 8.

Herein, in order to more specifically show the device structure, therewill be shown examples of the main dimensions and main parameters ofeach part of the device (see FIGS. 2 and 4). Namely, the width Wa of thelinear active cell region is about 1.0 micrometer, and the width Wi ofthe linear inactive cell region is about 2.5 micrometers (the width Waof the linear active cell region is desirably narrower than the width Wiof the linear inactive cell region, and the value of “Wi/Wa” is inparticular preferably within the range of, for example, 2 to 3). Thecontact width is about 1.0 micrometer; the trench width is about 0.7micrometer (in particular preferably 0.8 micrometer or less); the trenchdepth is about 3 micrometers; the depth of the N+ type emitter region 12is about 0.6 micrometer; and the depth of the P type body region 15(channel region) is about 1.2 micrometers. The depth of the P typefloating region 16 is about 4.5 micrometers; the thickness of the N typefield stop region 19 is about 1.5 micrometers; the thickness of the P+type collector region is about 0.5 micrometer; and the thickness of thesemiconductor substrate 2 is about 120 micrometers (herein, an exampleof a breakdown voltage of about 1200 volts is shown). Incidentally, thethickness of the semiconductor substrate 2 highly depends upon thebreakdown voltage. Therefore, with a breakdown voltage of 600 volts, thethickness is, for example, about 70 micrometers. With a breakdownvoltage of 400 volts, the thickness is, for example, about 40micrometers. Further, the recess depth in the top surface of the trenchgate electrode 14 is, for example, about 0.4 micrometer, and thedistance between the opposite-side trenches in the linear active cellregion 40 a (the distance between the inner sides of the trenches) is,for example, about 0.3 micrometer. The thickness of the P+ type bodycontact region 25 is, for example, about 0.4 micrometer; and thethickness of the P+ type buried body contact region is, for example,about 0.5 micrometer. The width of the active section 40 aa in thelinear active cell region 40 a is, for example, about 0.4 micrometer.Although the width of the inactive section 40 ai highly depends upon thevalue of the required saturation current, it is, for example, about 10micrometers. Whereas, the resistivity of the N− type drift region 20 is,for example, about 70 Ωcm.

The width of the active section 40 aa is preferably 0.5 micrometer orless. In this case, the running distance of the hole passing through theP type body region 15 under the N+ type emitter region 12 is estimatedas 0.25 micrometer or less, and is at an unproblematic level in view ofthe latch-up resistance.

Incidentally, also in the following examples and the examples of Section1, the dimensions of respective corresponding portions are roughly thesame as those herein shown, and hence a description thereon will not berepeated.

3. Explanation of Main Manufacturing Process Corresponding toManufacturing Method of the Narrow Active Cell IE Type Trench Gate IGBTof the One Embodiment of the Present Invention (Mainly FIGS. 10 to 24)

In this section, there will be shown one example of the manufacturingmethod of the device structure described in Section 2. Below, adescription will be mainly given to the cell region 10. However, for theperipheral parts and the like, if required, a reference will be made toFIG. 1, 2, 4, or the like.

FIG. 10 is a device cross-sectional view in a manufacturing step (holebarrier region introduction step) corresponding to FIG. 7 forillustrating a manufacturing method corresponding to the devicestructure of the one embodiment of the present invention. FIG. 11 is adevice cross-sectional view in a manufacturing step (P type floatingregion introduction step) corresponding to FIG. 7 for illustrating amanufacturing method corresponding to the device structure of the oneembodiment of the present invention. FIG. 12 is a device cross-sectionalview in a manufacturing step (trench processing hard mask depositionstep) corresponding to FIG. 7 for illustrating a manufacturing methodcorresponding to the device structure of the one embodiment of thepresent invention. FIG. 13 is a device cross-sectional view in amanufacturing step (trench hard mask processing step) corresponding toFIG. 7 for illustrating a manufacturing method corresponding to thedevice structure of the one embodiment of the present invention. FIG. 14is a device cross-sectional view in a manufacturing step (trenchprocessing step) corresponding to FIG. 7 for illustrating amanufacturing method corresponding to the device structure of the oneembodiment of the present invention. FIG. 15 is a device cross-sectionalview in a manufacturing step (trench processing hard mask removing step)corresponding to FIG. 7 for illustrating a manufacturing methodcorresponding to the device structure of the one embodiment of thepresent invention. FIG. 16 is a device cross-sectional view in amanufacturing step (drive-in diffusion and gate oxidation step)corresponding to FIG. 7 for illustrating a manufacturing methodcorresponding to the device structure of the one embodiment of thepresent invention. FIG. 17 is a device cross-sectional view in amanufacturing step (gate polysilicon etching back step) corresponding toFIG. 7 for illustrating a manufacturing method corresponding to thedevice structure of the one embodiment of the present invention. FIG. 18is a device cross-sectional view in a manufacturing step (P type bodyregion and N+ type emitter region introduction step) corresponding toFIG. 7 for illustrating a manufacturing method corresponding to thedevice structure of the one embodiment of the present invention. FIG. 19is a device cross-sectional view in a manufacturing step (P+ type bodycontact region and P+ type buried body contact region introduction step)corresponding to FIG. 8 for illustrating a manufacturing methodcorresponding to the device structure of the one embodiment of thepresent invention. FIG. 20 is a device cross-sectional view in amanufacturing step (interlayer insulation film deposition step)corresponding to FIG. 7 for illustrating a manufacturing methodcorresponding to the device structure of the one embodiment of thepresent invention. FIG. 21 is a device cross-sectional view in amanufacturing step (contact hole formation step) corresponding to FIG. 7for illustrating a manufacturing method corresponding to the devicestructure of the one embodiment of the present invention. FIG. 22 is adevice cross-sectional view in a manufacturing step (surface metaldeposition step) corresponding to FIG. 7 for illustrating amanufacturing method corresponding to the device structure of the oneembodiment of the present invention. FIG. 23 is a device cross-sectionalview in a manufacturing step (back surface girding and back surfaceimpurity introduction step) corresponding to FIG. 7 for illustrating amanufacturing method corresponding to the device structure of the oneembodiment of the present invention. FIG. 24 is a device cross-sectionalview in a manufacturing step (back surface metal electrode formationstep) corresponding to FIG. 7 for illustrating a manufacturing methodcorresponding to the device structure of the one embodiment of thepresent invention. Based on these, a description will be give to themain manufacturing process corresponding to the method for manufacturingthe narrow active cell IE type trench gate IGBT of the one embodiment ofthe present invention.

First, there is prepared a 200-diameter wafer (which may be each waferwith various diameters such as a diameter of 150, a diameter of 100, adiameter of 300, and a diameter of 450) of N− type silicon singlecrystal (e.g., phosphorus concentration: about 2×10¹⁴/cm³). Herein, forexample, a wafer by a FZ (Floating Zone) method is most preferable.However, a wafer by a CZ (Czochralski) method is also acceptable. Thisis because the wafer by the FZ method more readily provides ahigh-resistance wafer with a relatively higher quality, and more stableconcentration. On the other hand, annealing of a CZ crystal at around450 degrees centigrade generates thermal donors. This unfavorablyresults in an increase in substantial N type impurity capacity.Therefore, in this case, among the CZ crystals, those by the MCZ(Magnetic Field Applied CZ) method, having a relatively lower oxygenconcentration are preferably used. Among the MCZ crystals, the crystalsby, particularly, the HMCZ (Horizontal MCZ) method, the CMCZ (Cusp MCZ)method, and the like are particularly preferable. The oxygenconcentration of the low oxygen MCZ crystal is generally about from3×10¹⁷/cm³ to 7×10¹⁷/cm³. In contrast, the oxygen concentration of theFZ (Floating Zone) crystal is generally about 1×10¹⁶/m³, and the oxygenconcentration of a general CZ crystal not using the magnetic field isgenerally about 1×10¹⁸/cm³.

For the IE type trench gate IGBT of each embodiment of the presentinvention, even the crystals by the CZ method enables device designcommonly allowable as a product. This is due to the following: for theIGBT enhanced in IE effect, the overall hole distribution is relativelyflat in the ON state for the front surface-side hole accumulationeffect; accordingly, even when a variation is caused in crystalresistivity, the effect exerted on the switching loss is small.Incidentally, the range of the resistivity of the high resistance CZcrystal particularly suitable to an IGBT is the range from about 20 Ωcmto about 85 Ωcm, for example, when the breakdown voltage is assumed tobe within the range of from about 600 volts to 1200 volts.

Herein, in the IGBT, use of the CZ crystal has a merit of highmechanical strength and high thermal distortion resistance as distinctfrom the FZ crystal low in oxygen concentration. Further, as comparedwith the FZ crystal, the CZ crystal also has a merit of relative ease inincrease in diameter of the wafer. Further, with an increase indiameter, the importance of the problem of the thermal stress increases.Accordingly, use of the CZ crystal is more advantageous from theviewpoint of the countermeasure against thermal stress. Application ofthe structure of the present invention enables the FZ crystal and the CZcrystal to be used properly according to the situation.

Then, as shown in FIG. 10, almost entirely over the front surface 1 a(first main surface) of the semiconductor wafer 1, an N type holebarrier region introducing resist film 31 is formed by coating or thelike, and is patterned by general lithography. Using the patterned Ntype hole barrier region introducing resist film 31 as a mask, forexample, by ion implantation, N type impurities are introduced into asemiconductor substrate is (N− type single crystal silicon substrate) onthe front surface 1 a (first main surface) side of the semiconductorwafer 1, thereby to form an N type hole barrier region 24. As the ionimplantation conditions at this step, the following can be shown aspreferable ones: for example, ion species: phosphorus, dose amount:about 6×10¹²/cm², and implantation energy: about 80 KeV. Then, theresist film 31 which has become unnecessary is removed by ashing or thelike. Thus, the introduction of the N type hole barrier region 24 beforethe formation of the trench is advantageous for controlling the depthand the expansion in the lateral direction.

Then, as shown in FIG. 11, almost entirely over the front surface 1 a ofthe semiconductor wafer 1, a P type floating region introducing resistfilm 37 is formed by coating or the like, and is patterned by generallithography. Using the patterned P type floating region introducingresist film 37 as a mask, for example, by ion implantation, P typeimpurities are introduced into the semiconductor substrate is on thefront surface 1 a (first main surface) side of the semiconductor wafer1, thereby to form a P type floating region 16. As the ion implantationconditions at this step, the following can be shown as preferable ones:for example, ion species: boron, dose amount: about 3.5×10¹³/cm², andimplantation energy: about 75 KeV. Then, the resist film 37 which hasbecome unnecessary is removed by ashing or the like. Then, if required,activation annealing or the like is carried out (e.g., 900 degreescentigrade, about 30 minutes). Incidentally, at the time of introductionof the P type floating region 16, the cell peripheral junction region 35and the floating field ring 36 of FIG. 2 are also simultaneouslyintroduced. Thus, the introduction of the P type floating region 16before the formation of the trench is advantageous for controlling thedepth and the expansion in the lateral direction. Incidentally, it isnaturally understood that the timings of introduction of the N type holebarrier region 24 and the P type floating region 16 are reversible.

Then, as shown in FIG. 12, almost entirely over the front surface 1 a ofthe semiconductor wafer 1, for example, by CVD (Chemical VaporDeposition), there is deposited a trench forming hard mask film 32 suchas a silicon oxide type insulation film (e.g., with a thickness of about450 nm).

Then, as shown in FIG. 13, almost entirely over the front surface 1 a ofthe semiconductor wafer 1, a trench hard mask film processing resistfilm 33 is formed by coating or the like, and is patterned by generallithography. Using the patterned trench hard mask film processing resistfilm 33 as a mask, for example, by dry etching, the trench forming hardmask film 32 is patterned. Then, the resist film 33 which has becomeunnecessary is removed by ashing or the like.

Then, as shown in FIG. 14, using the patterned trench forming hard maskfilm 32, for example, a trench 21 is formed by anisotropic dry etching.As the gas type for the anisotropic dry etching, for example, Cl₂/O₂type gases can be shown as preferable ones.

Then, as shown in FIG. 15, by wet etching using, for example, ahydrofluoric acid type silicon oxide film etchant, there is removed thetrench forming hard mask film 32 which has become unnecessary.

Then, as shown in FIG. 16, the P type floating region 16 and the N typehole barrier region 24 are subjected to drive-in diffusion (e.g., 1200degrees centigrade, about 30 minutes). Thus, after the formation of thetrench, the P type floating region 16 and the N type hole barrier region24 are subjected to drive-in diffusion. This is advantageous forcontrolling the depth, and the expansion in the lateral direction.

Subsequently, for example, by thermal oxidation or CVD, or both thereof,almost entirely over the front surface 1 a of the semiconductor wafer 1and the inner surface of the trench 21, there is formed a gateinsulation film 22 (e.g., a thickness of about 120 nm).

Then, as shown in FIG. 17, a doped poly-silicon film 27 doped withphosphorus (e.g., a thickness of about 600 nm) is deposited in such amanner as to fill the trench 21 almost entirely over the front surface 1a of the semiconductor wafer 1 over the gate insulation film 22 and theinner surface of the trench 21 by, for example, CVD. Then, for example,by dry etching (e.g., gas type being SF₆), the polysilicon film 27 isetched back, thereby to form a trench gate electrode 14 in the trench21.

Then, as shown in FIG. 18, over the front surface 1 a of thesemiconductor wafer 1, a P type body region introducing resist film 38is formed by general lithography. Using the P type body regionintroducing resist film 38 as a mask, for example, by ion implantation,P type impurities are introduced into almost the entire surface of thecell region 10, and other necessary portions, thereby to form a P typebody region 15. As the ion implantation conditions at this step, thefollowing can be shown as preferable ones: for example, ion species:boron, dose amount: about 2×10¹³/cm², and implantation energy: about 250KeV. Then, the P type body region introducing resist film 38 which hasbecome unnecessary is removed by ashing or the like. Then, the P typebody region 15 is subjected to drive-in diffusion (e.g., 1000 degreescentigrade, about 100 minutes). Incidentally, after drive-in diffusionof the P type floating region 16 and the N type hole barrier region 24,the P type body region 15 is introduced. This is effective for controlof the profile and the like.

Then, over the front surface 1 a of the semiconductor wafer 1, an N+type emitter region introducing resist film 39 is formed by generallithography. Using the N+ type emitter region introducing resist film 39as a mask, for example, by ion implantation, N type impurities areintroduced into almost the entire surface of the top surface of the Ptype body region 15 in the active section 40 aa of the linear activecell region 40 a, thereby to form the N+ type emitter region 12. Interms of the feature of the structure of the present invention, thetrench gate electrode 14 front surface is recessed to a slightly deepposition (e.g., about 0.40 micrometer) from the front surface.Accordingly, the N+ type emitter region 12 is also required to be formedto a relatively deeper position correspondingly. As the ion implantationconditions at this step, the following two-stage ion implantation can beshown as the preferable one: for example, ion species: phosphorus, doseamount: about 1×10¹⁴/cm², and implantation energy: about 175 KeV, and inaddition to these, ion species: arsenic, dose amount: about 5×10¹⁵/cm²,and implantation energy: about 80 KeV. Then, the N+ type emitter regionintroducing resist film 39 which has become unnecessary is removed byashing or the like.

Then, as shown in FIG. 19, over the front surface 1 a of thesemiconductor wafer 1, an introducing resist film 56 such as a P+ typebody contact region is formed by general lithography. Using the P+ typebody contact region, etc., introducing resist film 56 as a mask, forexample, by ion implantation, P type impurities are introduced intoalmost the entire surface of the top surface of the P type body region15 in the inactive section 40 ai of the linear active cell region 40 a,thereby to form a P+ type body contact region 25. As the ionimplantation conditions at this step, the following can be shown as thepreferable ones: for example, ion species: BF₂, dose amount: about5×10¹⁵/cm², and implantation energy: about 80 KeV.

Then, using the P+ type body contact region, etc., introducing resistfilm 56 as a mask, for example, by ion implantation, P type impuritiesare introduced into almost the entire surface of the top surface of theP type body region 15 in the inactive section 40 ai of the linear activecell region 40 a, thereby to form a P+ type buried body contact region55. As the ion implantation conditions at this step, the following canbe shown as the preferable ones: for example, ion species: boron, doseamount: about 3×10¹⁵/cm², and implantation energy: about 80 KeV. Then,the P+ type body contact region, etc., introducing resist film 56 whichhas become unnecessary is removed by ashing or the like. Stillthereafter, the N+ type emitter region 12, the P+ type body contactregion 25, and the P+ type buried body contact region 55 are subjectedto activation annealing (e.g., 950 degrees centigrade, about 60minutes). Incidentally, it is naturally understood that the order ofintroduction of the N+ type emitter region 12, the P+ type body contactregion 25, and the P+ type buried body contact region 55 can be replacedwith each other. The introduction of the N+ type emitter region 12, theP+ type body contact region 25, and the P+ type buried body contactregion 55 is carried out after drive-in diffusion of the P type bodyregion 15. This is effective for controlling the profiles thereof.Further, the P+ type buried body contact region 55 is not essential.However, the presence of the P+ type buried body contact region 55 iseffective for the improvement of the latch-up resistance. Further, theP+ type body contact region 25 and the P+ type buried body contactregion 55 can also be formed by one-time ion implantation. However,two-stage ion implantation controls the concentration distribution moresimply, and hence is particularly suitable for the improvement of thelatch-up resistance.

Then, as shown in FIG. 20, almost entirely over the front surface 1 a ofthe semiconductor wafer 1, for example, by CVD, as an interlayerinsulation film 26, there is deposited, for example, a PSG(phosphosilicate glass) film (the thickness is, for example, about 600nm). Preferable examples of the material for the interlayer insulationfilm 26 may include, other than the PSG film, BPSG (borophosphosilicateglass) film, NSG (non-doped silicate glass) film, and SOG(spin-on-glass) film, or composite films thereof.

Then, as shown in FIG. 21, over the front surface 1 a of thesemiconductor wafer 1 over the interlayer insulation film 26, a contacttrench forming resist film is formed by general lithography.Subsequently, for example, by anisotropic dry etching (gas type being,for example, Ar/CHF₃/CF₄), there is formed a contact trench 11 (or acontact hole). Then, the resist film which has become unnecessary isremoved by ashing or the like.

Then, as shown in FIG. 22, by sputtering or the like, for example, thereis formed an aluminum type electrode film 8 (to be a metal emitterelectrode 8). Specifically, for example, the following procedure iscarried out. First, for example, by sputtering deposition, almostentirely over the front surface 1 a of the semiconductor wafer 1, as abarrier metal film, there is formed a TiW film (e.g., a thickness ofabout 200 nm) (by a later heat treatment, a large portion of titanium inthe TiW film moves to the silicon interface to form silicide, whichcontributes the improvement of the contact characteristics, but theprocess is complicated, and hence is not shown in the drawing).

Subsequently, for example, about 30-minute silicide annealing is carriedout in a nitrogen atmosphere at about 650 degrees centigrade.Subsequently, almost entirely over the barrier metal film, an aluminumtype metal film including aluminum as a main component (e.g., siliconadded in an amount of several percent, and the balance being aluminum)(e.g., with a thickness of about 5 micrometers) is formed in such amanner as to fill the contact trench 11, for example, by sputteringdeposition. Subsequently, by general lithography, the metal emitterelectrode 8 including an aluminum type metal film and a barrier metalfilm is patterned (as the gas type for dry etching, for example,Cl₂/BCl₃). Further, as a final passivation film, for example, an organicfilm including polyimide as a main component (e.g., with a thickness ofabout 2.5 micrometers) is coated almost entirely over the device surface1 a of the wafer 1. By general lithography, the emitter pad 9, the gatepad 6, and the like of FIG. 5 are opened.

Then, the back surface 1 b of the wafer 1 is subjected to a backgrinding treatment (if required, chemical etching or the like forremoving the damage of the back surface is also carried out). As aresult, the original wafer thickness of, for example, about 800micrometers (as the preferable range, about from 1000 to 450micrometers) is, if required, reduced to, for example, about 200 to 30micrometers. For example, when the breakdown voltage is assumed to beabout 1200 volts, the final thickness is about 120 micrometers.

Then, as shown in FIG. 23, N type impurities are introduced into almostthe entire surface of the back surface 1 b of the semiconductor wafer 1,for example, by ion implantation, thereby to form an N type field stopregion 19. Herein, as the ion implantation conditions, the following canbe shown as the preferable ones: for example, ion species: phosphorus,dose amount: about 7×10¹²/cm², and implantation energy: about 350 KeV.Then, if required, for impurity activation, the back surface 1 b of thewafer 1 is subjected to laser annealing or the like. Then, N typeimpurities are introduced into almost the entire surface of the backsurface 1 b of the semiconductor wafer 1, for example, by ionimplantation, thereby to form a P+ type collector region 18. Herein, asthe ion implantation conditions, the following can be shown as thepreferable ones: for example, ion species: boron, dose amount: about1×10¹³/cm², and implantation energy: about 40 KeV. Then, if required,for impurity activation, the back surface 1 b of the wafer 1 issubjected to laser annealing or the like. Herein, for the activationannealing of back surface ion implantation, the laser annealingconditions are optimized. As a result, the crystal defects generated bythe back surface ion implantation at the portion in proximity to theboundary between the N type field stop region 19 and the N− type driftregion 20 can be intentionally allowed to remain. The remaining crystaldefects function as a local lifetime control layer, and contributes tothe improvement of the trade-off characteristics of switchingperformance-ON voltage. Herein, as the annealing conditions (laserapplication conditions), the following can be shown as the preferableones: for example, annealing method: laser is applied from the backsurface 1 b side of the wafer 1, wavelength: 527 nm, pulse width: about100 ns, energy density: about 1.8 J/cm², application system: 2-pulsesystem, delay time between both pulses: about 500 ns, and pulse overlapratio: about 66%.

Then, as shown in FIG. 24, for example, by sputtering deposition, ametal collector electrode 17 is formed over almost the entire surface ofthe back surface 1 b of the semiconductor wafer 1 (for specific details,see FIG. 25 and its explanation). Then, by dicing or the like, divisioninto the chip regions of the semiconductor wafer 1 is performed, and, ifrequired, sealing in a package is performed, resulting in the completionof the device.

4. Detailed Description on Back Surface Side Device Structure of theNarrow Active Cell IE Type Trench Gate IGBT Of the One Embodiment of thePresent Invention, or Explanation Of Modified Example (Aluminum-DopedStructure) (Mainly FIG. 25)

The examples described in this section relate to the back surface sidestructure of the semiconductor substrate. However, other examples thanthose in this section all relate to the front surface side structure ofthe semiconductor substrate. Therefore, the examples of this section areapplicable to all other examples than those in this section. Further, itis naturally understood that they are also applicable to IGBTs havingother general front surface side structure, and the like.

In this section, for convenience of description, the device structurewill be described in accordance with the example of Section 2. As forthe process, a brief description will be given by reference to Section3.

Incidentally, below, the IE type trench gate IGBT will be specificallydescribed. It is naturally understood that the back surface structure isnot limited to the IE type IGBT and the trench gate IGBT, but is alsoapplicable to IGBTs in other forms, and the like.

FIG. 25 is a local detailed cross-sectional view of the device backsurface for a detailed description on the back surface side devicestructure of the narrow active cell IE type trench gate IGBT of the oneembodiment of the present invention, or for illustrating the devicestructure and the manufacturing method of a modified example(aluminum-doped structure). Based on this, an explanation will be givento the detailed description on the back surface side device structure ofthe narrow active cell IE type trench gate IGBT of the one embodiment ofthe present invention or a modified example (aluminum-doped structure).

FIG. 25 shows a cross-sectional enlarged view of the back side and itsvicinity of the semiconductor chip 2 of FIG. 7 (a schematic view of thestructure in the vicinity of the back side enlarged in the thicknessdirection of the chip). As shown in FIG. 25, in the semiconductor regionat the bottom end of the P+ type collector region 18 on the back surfaceside of the semiconductor substrate 2, there is arranged a relativelythin P type semiconductor region (with a thickness of, for example,about 0.04 to 0.1 micrometer), namely, an aluminum doped region 30. Theimpurity concentration (e.g., about 1×10¹⁹/cm³) is higher than theimpurity concentration of the P+ type collector region 18. A metalcollector electrode 17 is formed in contact with the aluminum dopedregion 30 over the back surface 1 b of the semiconductor substrate 2.One example thereof will be shown as the following configuration fromthe side closer to the semiconductor substrate 2. Namely, there are analuminum back surface metal film 17 a (e.g., with a thickness of about600 nm) which is an impurity source of the aluminum doped region 30, atitanium back surface metal film 17 b (e.g., with a thickness of about100 nm), a nickel back surface metal film 17 c (e.g., with a thicknessof about 600 nm), and a gold back surface metal film 17 d (e.g., with athickness of about 100 nm).

Then, the manufacturing method will be described briefly. In the processof FIG. 24 in Section 3, namely, during sputtering deposition, thealuminum back surface metal film 17 a, the titanium back surface metalfilm 17 b, the nickel back surface metal film 17 c, and the gold backsurface metal film 17 d are sequentially subjected to sputteringdeposition. By the heat generated at this step, aluminum is introducedinto the silicon substrate, thereby to form the aluminum doped region30. Then, by dicing or the like, division into chip regions of thesemiconductor wafer 1 is performed, resulting in the state as shown inFIG. 7 (FIG. 7 does not clearly show the detailed structure).

In each embodiment of the present invention, there is adopted astructure in which, in the ON state, holes are accumulated on theemitter side to promote the injection of electrons. On the other hand,for the PN diode on the back surface collector side, conversely, thereis adopted a diode resulting in a low injection efficiency, thereby toachieve a lower switching loss. Namely, there is adopted a transparentemitter. Herein, in order to form the back surface diode with a lowinjection efficiency, it is effective to reduce the ratio of the carrierconcentration “Qp” to the P+ type collector region 18 and the carrierconcentration “Qn” of the N type field stop region 19 (which will behereinafter referred to as a “carrier concentration ratio”), namely,“(Qp/Qn)”. However, to that end, when the carrier concentration “Qp” ofthe P+ type collector region 18 is excessively reduced, thecharacteristics of the back surface metal contact are deteriorated.Thus, in this example, there is arranged the aluminum doped region 30higher in impurity concentration than the P+ type collector region 18introduced from the back-surface aluminum film. As the carrierconcentration ratio, for example, about 1.5 (the range of, e.g, about1.1 to 4) can be shown as the preferable one capable of optimizing thetrade-off performance of switching performance-ON voltage performance.In each embodiment of the present invention, there is adopted astructure in which, in the ON state, holes are accumulated on theemitter side to promote the injection of electrons. At this step,electrons injected from the front surface side reach the back surfacecollector side, and promote injection of holes from the back surface PNdiode. Further, the injected holes reach the front surface, and promoteinjection of electrons from the front surface side. When each embodimentof the present invention is employed, such a positive feedbackphenomenon facilitates the occurrence of the conductivity modulation ofthe N-drift region 20. For this reason, it becomes possible to implementa device less likely to undergo an increase in ON voltage even when thePN diode on the back surface collector side has a specificationresulting in lower injection efficiency. When the switching performanceis regarded as important, the case where the “(Qp/Qn)” is set at 1 orless is also assumed. However, even in that case, the effect of thesurface structure of the present invention can suppress a sharp increasein ON voltage.

5. Explanation of Modified Example 1 Regarding the Front Surface SideDevice Structure of the Narrow Active Cell IE Type Trench Gate IGBT ofthe One Embodiment of the Present Invention (N+ Type Surface FloatingRegion & P+ Type Surface Floating Region Addition Structure) (MainlyFIGS. 26 to 28)

The example described in this section is, for example, a modifiedexample of the planar layout of FIG. 6.

FIG. 26 is an enlarged top view corresponding to FIG. 6, forillustrating Modified Example 1 (N+ type surface floating region & P+type surface floating region addition structure) regarding the surfaceside device structure of the narrow active cell IE type trench gate IGBTof the one embodiment of the present invention. FIG. 27 is a devicecross-sectional view corresponding to a F-F′ cross section of FIG. 26.FIG. 28 is a device cross-sectional view corresponding to a G-G′ crosssection of FIG. 26. Based on these, a description will be given toModified Example 1 (N+ type surface floating region & P+ type surfacefloating region addition structure) regarding the surface side devicestructure of the narrow active cell IE type trench gate IGBT of the oneembodiment of the present invention.

As shown in FIG. 26, as distinct from FIG. 6, not only in the linearactive cell region 40 a, but also in the portion of a linear inactivecell region 40 i corresponding to the active section 40 aa, there isarranged an N+ type surface floating region 12 i (first conductivitytype surface floating region) corresponding to the N+ type emitterregion 12. Namely, the N+ type surface floating region 12 i is formed inthe same process as that for, for example, the N+ type emitter region12, simultaneously. As a result, the linear inactive cell region 40 i isdivided into a first conductivity type floating region formation sectionin which the N+ type surface floating region 12 i is formed in thelength direction thereof, and a first conductivity type floating regionnon-formation section in which the N+ type surface floating region 12 iis not formed.

Some of electrons injected from the MOSFET portion in the IGBT passthrough the accumulation layer formed at the N type layer portion of thetrench sidewall and the inversion layer formed at the P type sidewallportion, and also reach the N+ type surface floating region 12 i, to beinjected into the P type floating region 16. When the IGBT turns off inthis state, the electrons recombine with holes remaining in the P typefloating region 16 to be annihilated. As a result, it is possible toreduce the switching loss at the OFF time.

Further, similarly, as distinct from FIG. 6, not only in the linearactive cell region 40 a, but also in the portion of a linear inactivecell region 40 i corresponding to the active section 40 aa, there arearranged regions corresponding to the P+ type body contact region 12 andthe P+ type buried body contact region 55. Namely, the regions are a P+type surface floating region 25 i (second conductivity type surfacefloating region) and a P+ type buried floating region 55 i.

Therefore, the F-F′ cross section of FIG. 26 is roughly equal to FIG. 7,except that as shown in FIG. 27, in the front surface 1 a of thesemiconductor substrate of the active section 40 aa in the linearinactive cell region 40 i, there is arranged the N+ type surfacefloating region 12 i.

On the other hand, the G-G′ cross section of FIG. 26 is equal to FIG. 8,except that as shown in FIG. 28, also in the front surface region of theP type body region 15 in the linear inactive cell region 40 i, there arearranged a P+ type surface floating region 25 i (second conductivitytype surface floating region) and a P+ type buried floating region 55 icorresponding to the P+ type body contact region 12 and the P+ typeburied body contact region 55.

Such a structure has a merit of forming the N+ type emitter regionintroducing resist film 39 and the P+ type body contact region, etc.,introducing resist film 56 in a relatively simple structure crossing thetrench 21. Namely, the structure has a merit of increasing the processmargin in that there is eliminated the necessity of allowing the ends ofthe resist film patterns to extend along the trench. Further, also forthis case, the structure is not limited to fully crossing the linearinactive cell region 40 i. It is also acceptable that the ends of theresist film patterns of the N+ type emitter region introducing resistfilm 39 and the P+ type body contact region, etc., introducing resistmay be formed inside the linear inactive cell region 40 i.

6. Explanation of Modified Example 2 Regarding the Front Surface SideDevice Structure of the Narrow Active Cell IE Type Trench Gate IGBT ofthe One Embodiment of the Present Invention (Simplified Active CellStructure) (Mainly FIG. 29)

The unit cell structure described in this section is the one obtained byomitting the P type floating region 16 and the N type hole barrierregion 24 in the unit cell structure in FIG. 7.

FIG. 29 is a device cross-sectional view corresponding to the C-C′ crosssection of FIG. 6 corresponding to FIG. 7 for illustrating ModifiedExample 2 (simplified active cell structure) regarding the surface sidedevice structure of the narrow active cell IE type trench gate IGBT ofthe one embodiment of the present invention. Based on this, adescription will be given to Modified Example 2 (simplified active cellstructure) regarding the front surface side device structure of thenarrow active cell IE type trench gate IGBT of the one embodiment of thepresent invention.

As shown in FIG. 27, in this example, in the unit cell structure in FIG.7, the P type floating region 16 and the N type hole barrier region 24are omitted. Therefore, the hole concentration of the N− type driftregion 20 portion of the linear active cell region 40 a tends to bereduced as compared with the structure of FIG. 7. For example, when thelinear active cell region 40 a is sufficiently narrow, and when thedepth of the trench 21 is sufficiently deep, it becomes effective toadopt the structure of FIG. 29. Namely, it is possible to simplify thedevice structure and the impurity doping step. Further, there isimplemented a structure advantageous in the case not for use in whichimportance is placed on a low ON voltage, but for use in which theswitching performance is desired to be made higher.

7. Explanation of Modified Example 3 Regarding the Front Surface SideDevice Structure of the Narrow Active Cell IE Type Trench Gate IGBT ofthe One Embodiment of the Present Invention (Hole Collector CellAddition Structure) (Mainly FIGS. 30 to 35)

The example described in this section is a modified example relative tothe basic device structure (mainly FIG. 2) described in Section 1.Therefore, other views such as FIGS. 1, and 3 to 29 also apply to thisexample with corresponding changes added thereto, respectively, or asthey are.

FIG. 30 is a device schematic cross-sectional view of the A-A′ crosssection of the cell region end cut-out region R1 of FIG. 1 correspondingto FIG. 2 for illustrating Modified Example (hole collector celladdition structure) regarding the surface side device structure of thenarrow active cell IE type trench gate IGBT of the one embodiment of thepresent invention. FIG. 31 is an enlarged top view of the linear unitcell region and its periphery R5 of FIG. 1 for illustrating ModifiedExample (hole collector cell addition structure) regarding the surfaceside device structure of the narrow active cell IE type trench gate IGBTof the one embodiment of the present invention. FIG. 32 is an enlargedtop view corresponding to FIG. 6 for illustrating Modified Example 3(hole collector cell addition structure) regarding the surface sidedevice structure of the narrow active cell IE type trench gate IGBT ofthe one embodiment of the present invention. FIG. 33 is a devicecross-sectional view corresponding to a H-H′ cross section of FIG. 32.FIG. 34 is a device cross-sectional view corresponding to a J-J′ crosssection of FIG. 32. FIG. 35 is a device cross-sectional viewcorresponding to a K-K′ cross section of FIG. 32. Based on these, adescription will be given to Modified Example 3 (hole collector celladdition structure) regarding the front surface side device structure ofthe narrow active cell IE type trench gate IGBT of the one embodiment ofthe present invention.

(1) Explanation of Narrow Active Cell Type Unit Cell and Alternate ArraySystem (Mainly FIG. 30):

Then, FIG. 30 shows the X-X′ cross section of the cell region endcut-out region R1 of FIG. 1. As shown in FIG. 30, in the semiconductorregion (in this example, silicon single crystal region) of the backsurface 1 b (the back side main surface or the second main surface ofthe semiconductor substrate) of the chip 2, there is arranged the P+type collector region 18. Over the front surface, there is arranged themetal collector electrode 17. Between the N− type drift region 20 (firstconductivity type drift region) and the P+ type collector region 18forming the main part of the semiconductor substrate 2, there isarranged the N type field stop region 19.

On the other hand, in the semiconductor region on the front surface side1 a of the N− type drift region 20 (the front side main surface or thefirst main surface of the semiconductor substrate), there are arranged alarge number of trenches 21. Therein, trench gate electrodes 14 areembedded via the gate insulation film 22, respectively. Each trench gateelectrode 14 is coupled to the metal gate electrode 5 (specifically, themetal gate wire 7) or the emitter electrode 8 according to its function.

Further, the trenches 21 perform a function of defining respectiveregions. For example, a dummy cell region 34 is defined from oppositesides thereof by a pair of trenches 21. One trench 21 of these definesthe cell region 10 and the cell peripheral junction region 35. The cellperipheral junction region 35 is coupled via a P+ type body contactregion 25 p to the metal emitter electrode 8. Incidentally, in thepresent invention, unless otherwise specified, the thickness of the gateinsulation film 22 at any portion of the trench is assumed to be roughlyequal (however, it is not excluded that, if required, a given portion isdifferent in thickness from other portions). Thus, in the cellperipheral junction region 35 and the dummy cell region 34, an emittercontact is established. As a result, even when the width of the dummycell region 34 or the like is changed in view of process, it is possibleto prevent the reduction of the breakdown voltage.

In the semiconductor region on the front surface side 1 a of the N− typedrift region 20 outside the cell peripheral junction region 35, there isarranged a P type floating field ring 36. Over the front surface 1 a, afield plate 4 is arranged, and is coupled via a P+ type body contactregion 25 r to the floating field ring 36.

Then, the cell region 10 will be further described. The dummy cellregion 34 is basically equal in both structure and size to the linearactive cell region 40 a except for not having an N+ type emitter region12. A P+ type body contact region 25 d arranged in the front surface ofthe P type body region 15 is coupled to the metal emitter electrode 8.Further, the dummy cell region 34 can be basically formed in the samestructure as that of the hole collector cell (see FIG. 30).

Most of the inside region of the cell region 10 basically has arepeating structure of translational symmetry with the linear unit cellregion 40 as a unit cell (incidentally, symmetry in a strict sense isnot required. The same shall apply hereinafter). The linear unit cellregion 40 as the unit cell includes a linear inactive cell region 40 i,a linear active cell region 40 a on one side thereof, a linear holecollector cell region 40 c on the other side thereof, and, half-widthlinear inactive cell regions 40 i on opposite sides thereof. However,specifically, it can be seen that the linear active cell regions 40 aand the linear hole collector cell regions 40 c are alternately arrangedbetween the full-width linear inactive cell regions 40 i (see FIG. 31).Alternatively, it can also be seen that first linear unit cell regions40 f and second linear unit cell regions 40 s are alternately arrayed.

In the semiconductor surface region on the front side main surface 1 a(first main surface) side of the semiconductor substrate of the linearactive cell region 40 a, there is arranged the P type body region 15(second conductivity type body region). In the front surface thereof,there are arranged an N+ type emitter region 12 (first conductivity typeemitter region) and a P+ type body contact region 25. The N+ typeemitter region 12 and the P+ type body contact region 25 are coupled tothe metal emitter electrode 8. In the linear active cell region 40 a, inthe N− type drift region 20 under the P type body region 15, there isarranged an N type hole barrier region 24. Incidentally, the trench gateelectrodes 14 on the opposite sides of the linear active cell region 40a are electrically coupled to the metal gate electrode 5.

In contrast, the structure of the linear hole collector cell region 40 cis different in this example only in that there is no N+ type emitterregion 12, and in that the trench gate electrodes 14 on the oppositesides thereof are coupled to the emitter electrode 8, and, is equal inother respects including dimensions and the like to the linear activecell region 40 a.

On the other hand, in the front side main surface 1 a (first mainsurface) side semiconductor surface region of the semiconductorsubstrate in the linear inactive cell region 40 i, similarly, the P typebody region 15 is arranged. In the underlying N− type drift region 20,there is arranged a P type floating region 16 (second conductivity typefloating region) covering the lower ends of the trenches 21 on theopposite sides, and deeper than them. By arranging such a P typefloating region 16, it is possible to widen the width Wi of the linearinactive cell region without causing a sharp reduction of the breakdownvoltage. For example, even when the layout is adjusted in order tooptimize the characteristics such as the gate capacity and ON voltage,there is no fear of the reduction of the breakdown voltage, and thedegree of freedom for design can be ensured. Further, for example, whenthe concentration of the N type hole barrier region 24 is increased foroptimization, similarly, there is no effect on the breakdown voltage. Asa result of this, it becomes possible to effectively enhance the holeaccumulation effect. Incidentally, in the IE type trench gate IGBT,there is not formed a contact from the emitter electrode 8 to the P typefloating region 16. This is as follows: the direct hole discharge pathfrom the P type floating region 16 to the emitter electrode 8 isblocked, which results in an increase in hole concentration of the N−type drift region 20 (N base region) under the linear active cell region40 a; as a result, the electron concentration to be injected from theMOSFET into the N base region in the IGBT is improved, thereby to reducethe ON resistance.

In this example, the width Wa of the linear active cell region 40 a andthe width We of the linear hole collector cell region 40 c are setnarrower than the width Wi of the linear inactive cell region 40 i. Inthe present invention, this is referred to as a “narrow active cell typeunit cell”. Below, mainly, a device having the narrow active cell typeunit cell will be specifically described. However, the example hereindescribed is not limited thereto. It is naturally understood that theexample is also applicable to a device having a “non-narrow active celltype unit cell”.

In the example of FIG. 30, the linear active cell regions 40 a (or thelinear hole collector cell regions 40 c) and the linear inactive cellregions 40 i are alternately arrayed to form the linear unit cell region40. This configuration is referred to as an “alternate array system” inthe present invention. Below, unless otherwise specified, a descriptionwill be given on the premise of the alternate array system. However, itis naturally understood that the “non-alternate array system” is alsoacceptable.

In FIG. 30, a description was given to the outline of embodiments ofFIGS. 31 to 35 of the present invention (the main part and theperipheral part). However, in the following description, these aredivided into structural elements such as a cell part (cross-sectional orplanar structure), and a cell peripheral part to be described. However,it is naturally understood that these also provides the outlines tovarious modified examples.

(2) Explanation of Active Cell Two-Dimensional Thinned-Out Structure(Mainly FIG. 31)

FIG. 31 shows one example of the detailed planar structure of the linearunit cell region main part and its peripheral cut-out region R5 ofFIG. 1. As shown in FIG. 31, in the length direction of the linearactive cell region 40 a, for example, active sections 40 aa having agiven length are arranged at a given interval, between which there is aninactive section 40 ai not including the N+ type emitter region 12arranged therein. Namely, some portions in the length direction of thelinear active cell region 40 a locally and dispersively become theactive sections 40 aa. A further description will be given. In theactive section 40 aa of the linear active cell region 40 a, in almostthe entire region thereof, there is arranged the N+ type emitter region12. In the inactive section 40 ai of the linear active cell region 40 a,in almost the entire region thereof, there are arranged the P+ type bodycontact region 25 and the P+ type buried body contact region 55. On theother hand, in the linear hole collector cell region 40 c, in almost theentire region thereof, the P+ type body contact region 25 and the P+type buried body contact region 55 are arranged, and the N+ emitterregion 12 is not arranged. In the linear inactive cell region 40 i,similarly to others, in almost the entire region thereof, there arearranged the P type body region 15 and the P type floating region 16(second conductivity type floating region).

Incidentally, herein, “being distributed with a given length at a giveninterval” means “being periodical”. However, “being substantiallyperiodical” corresponds to the local and dispersive distribution.However, “being local and dispersive” is “being wider than that” anddoes not necessarily mean “being periodical or quasi-periodical”.

(3) Detailed Description of Layout and Device Structure In which ActiveCells are Alternately Replaced with Hole Collector Cells (Mainly FIGS.32 to 35):

The structures of the linear active cell region 40 a and the linearinactive cell region 40 i are the same as those shown in FIGS. 4, and 6to 9. Below, only the linear hole collector cell region 40 c will bedescribed.

As shown in FIG. 32, the trench buried electrodes 14 c on the oppositesides of the linear hole collector cell region 40 c are required to becoupled to the emitter potential. In this example, two (the trenchburied electrodes 14 c on the opposite sides) are coupled to each othervia, for example, a buried electrode coupling part 28 of a polysiliconfilm at the same layer (including an intra-trench electrode 14 i in thecoupling part trench 21 c). Over the buried electrode coupling part 28,there is arranged a contact part 11 c (contact hole) between emitterelectrode—buried electrode, via which, coupling is established with themetal emitter electrode 8. Then, the feature of the linear holecollector cell region 40 c is similar to that of the linear active cellregion 40 a, but is different in that the N+ type emitter region 12 isnot arranged, and in that the P+ type body contact region 25 and the P+type buried body contact region 55 are arranged in almost the entireregion except for the underlying part of the buried electrode couplingpart 28.

Then, FIG. 33 shows the H-H′ cross section of FIG. 32. As shown in FIG.33, the cross section is similar to the cross section (linear activecell region 40 a) of FIG. 7. However, in the cross section of the linearhole collector cell region 40 c, there is the buried electrode couplingpart 28 (polysilicon coupling part) in the overlying part. So the N+type emitter region 12 and the P type body region 15 are not introduced.This is for the following reason: in the step of FIG. 17, thepolysilicon film 27 over the linear hole collector cell region 40 c isleft; as a result, in the step of FIG. 18, impurities are not introducedunder the buried electrode coupling part 28. This also applies to FIG.34. Herein, the underlying part of the buried electrode coupling part 28is in the floating state. If the P type diffusion layer is not presentat all, in the OFF state, the electric field intensity concentrates tothe trench bottom end, resulting in the reduction of the breakdownvoltage. For this reason, into under the buried electrode coupling part28, the P type floating region 16 is desirably introduced. The P typefloating region 16 has been subjected to ion implantation at the stepbefore the formation of the buried electrode, and hence can be arrangedunder the buried electrode coupling part 28. As a result, even if thelinear inactive cell region 40 i is set with any dimensions, thebreakdown voltage can be ensured. This enables the design having thedegree of freedom according to the product requirements.

Then, FIG. 34 shows the J-J′ cross section of FIG. 32. As shown in FIG.34, the cross section is basically similar to FIG. 9, but is differentin that between the linear hole collector cell region 40 c and thelinear inactive cell region 40 i, there are a coupling part trench 21 cand a trench buried coupling part 14 i. Further, the cross section isalso different in that, for the same reason as the previous one, in thelinear hole collector cell region 40 c, there are no N+ type emitterregion 12, no P+ type body contact region 25, and no P+ type buried bodycontact region 55. Further, the coupling part trench 21 c efficientlyseparates the P type floating region 16 from the P+ type body contactregion 25 and the P+ type buried body contact region 55 coupled to themetal emitter electrode 8.

Then, FIG. 35 shows the K-K′ cross section of FIG. 32. As shown in FIG.35, the cross section is entirely equal to FIG. 8, except that thetrench gate electrode 14 is a trench buried electrode 14 c coupled tothe emitter potential.

The degree of the hole accumulation effect of the surface devicestructure depends upon the geometrical shape and the N type hole barrierregion 24. In other words, the linear active cell region 40 a and thelinear hole collector cell region 40 c do not cause a significantdifference for holes. In other words, the hole accumulation effect isequal, and accordingly, the IE effect is also equal. Thus, by replacingsome of a plurality of the linear active cell regions 40 a with thelinear hole collector cell regions 40 c, respectively, it is possible toreduce the trenches functioning as a gate capacity with the holeaccumulation effect still in the same state. In other words, it ispossible to prevent an increase in gate capacity even when cellshrinkage is achieved to the utmost in order to enhance the IE effect.

Further, when some of the linear active cell regions 40 a are replacedwith the linear hole collector cell regions 40 c, respectively, still inthat state, the absolute amount of the N+ type emitter region 12 perunit area is reduced, resulting in a smaller saturation current value.However, when the length of the inactive section 40 ai in the linearactive cell region 40 a is shortened, and the proportion occupied by theactive section 40 aa is increased and optimized, it is possible to keepthe value of the saturation current required as an IGBT for invertorsuse. In the main embodiment of the present invention, the linear layoutis basically adopted. Thus, the optimum design of the N+ type emitterregion 12 is easy. Further, for the IGBT using the related-arttechnology, substantial cell shrinkage is implemented. For this reason,even when the linear hole collector cell region 40 c is arranged,optimization of the layout in the linear active cell region 40 a canensure the saturation current required as the whole chip.

8. Supplementary Explanation on the Embodiment (Including ModifiedExamples) and Consideration on the Whole (Mainly FIG. 36)

FIG. 36 is an enlarged top view of the linear unit cell region and itsperiphery R5 of FIG. 1 for illustrating the outline of the devicestructure of the one embodiment of the present invention. Based on this,a description will be given to the supplementary explanation on theembodiment (including modified examples), and the consideration on thewhole thereof.

In an IE type IGBT, an attempt to enhance the IE effect requiresminimization of the interval between trenches. However, with a structureincluding substrate trenches for body contact (or substrate contacttrench), it is necessary to ensure the width of the substrate contacttrench. Thus, shrinkage is difficult. On the other hand, even a decreasein width of the trench itself does not lead to the improvement of the IEeffect. Rather, in order to ensure the thickness of the gate insulationfilm or the like, the with of the trench itself is desirably notreduced.

Thus, in the each embodiment (including modified examples), as shown inFIG. 36, in the two-dimensional thinned-out structure, over almost theentire surface of the active section 40 aa of the linear active cellregion 40 a, the N+ type emitter region 12 is spread, resulting in astructure including no P+ type body contact region 25.

Herein, from the viewpoint of ensuring the latch-up resistance, thewidth of the active section 40 aa is desirably as small as possible(e.g., about 0.5 micrometer or less). Incidentally, when the area of thewhole active sections 40 aa is desired to be increased, preferably, thewidth of each individual active section 40 aa is made as it is, and thepitch thereof is reduced (the number is increased). When the width feach individual active section 40 aa is simply increased too much, notonly the latch-up resistance is reduced, but also the short-circuit safeoperating area is also reduced.

9. Summary

Up to this point, the invention made by the present inventors wasspecifically described by way of embodiments. However, the presentinvention is not limited thereto. It is naturally understood thatvarious changes may be made within the scope not departing from the gistthereof.

For example, in the each embodiment, a specific description was given tothe example using doped poly-silicon or the like as the gate polysiliconmember. However, the present invention is not limited thereto. Thefollowing procedure is also acceptable: a nondoped poly-silicon film isapplied thereto; after deposition, necessary impurities are added by ionimplantation or the like.

Further, in the each embodiment, a description was given to the examplein which using a non-epitaxial wafer, after back grinding, ahigh-concentration impurity layer was formed from the back surface.However, the present invention is not limited thereto. It is naturallyunderstood that the present invention is also applicable to the onemanufactured using an epitaxial wafer.

What is claimed is:
 1. A narrow active cell IE type trench gate IGBTcomprising: (a) a silicon type semiconductor substrate having a firstmain surface and a second main surface; (b) an IGBT cell region arrangedon the first main surface side of the silicon type semiconductorsubstrate; (c) a plurality of linear active cell regions and a pluralityof linear inactive cell regions arranged in the IGBT cell region; (d) aplurality of active sections and a plurality of inactive sectionsalternately arrayed along the longitudinal direction of the each linearactive cell region; (e) a trench arranged in the first main surface ofthe silicon type semiconductor substrate, and at a boundary part betweenthe each linear active cell region and the each linear inactive cellregion; (f) a gate electrode arranged in the trench via an insulationfilm; (g) an emitter region having a first conductivity type, arrangedin a surface region on the first main surface side of the silicon typesemiconductor substrate, and over almost the entire region of the eachactive section; (h) a body contact region having a second conductivitytype, arranged in the surface region on the first main surface side ofthe silicon type semiconductor substrate, and in the each inactivesection; and (i) a metal emitter electrode arranged over the first mainsurface of the silicon type semiconductor substrate, and electricallycoupled to the emitter region and the body contact region.
 2. The narrowactive cell IE type trench gate IGBT according to claim 1, wherein thebody contact region is arranged over almost the entire region of theeach inactive section.
 3. The narrow active cell IE type trench gateIGBT according to claim 2, further comprising: (j) a second conductivitytype floating region arranged in the surface region on the first mainsurface side of the silicon type semiconductor substrate, and in almostthe entire region of the each linear inactive cell region, in such amanner as to extend to the bottom ends of the trenches on the oppositesides thereof.
 4. The narrow active cell IE type trench gate IGBTaccording to claim 3, further comprising: (k) a hole barrier regionhaving the first conductivity type, arranged in the surface region onthe first main surface side of the silicon type semiconductor substrate,and in almost the entire region of the each linear active cell region,to the same level of depth as that of the bottom ends of the trenches onthe opposite sides thereof.
 5. The narrow active cell IE type trenchgate IGBT according to claim 4, further comprising: (m) a buried bodycontact region having the second conductivity type, arranged in almostthe entire surface of the layer underlying the body contact region insuch a manner as to be in contact therewith.
 6. The narrow active cellIE type trench gate IGBT according to claim 5, wherein the intervalbetween the trenches on the opposite sides of the each linear activecell region is 0.35 micrometer or less.
 7. The narrow active cell IEtype trench gate IGBT according to claim 6, wherein the width in thelongitudinal direction of the each active section is 0.5 micrometer orless.
 8. The narrow active cell IE type trench gate IGBT according toclaim 7, further comprising: (n) a first conductivity type surfacefloating region arranged in the surface region on the first main surfaceside of the silicon type semiconductor substrate, and in the each linearinactive region at a position on the extension of the emitter region inthe adjacent linear active region.
 9. The narrow active cell IE typetrench gate IGBT according to claim 8, further comprising: (p) a secondconductivity type surface floating region arranged in the surface regionon the first main surface side of the silicon type semiconductorsubstrate, and in the each linear inactive region at a position on theextension of the body contact region in the adjacent linear activeregion.
 10. The narrow active cell IE type trench gate IGBT according toclaim 7, further comprising: (q) a hole collector cell region arrangedin such a manner as to alternately substitute for the linear active cellregions.
 11. The narrow active cell IE type trench gate IGBT accordingto claim 7, further comprising: (r) a drift region having the firstconductivity type, arranged from the inside to the first main surface inalmost the entire region of the silicon type semiconductor substrate;(s) a field stop region arranged on the second main surface side of thedrift region in almost the entire region of the silicon typesemiconductor substrate, having the first conductivity type, and havinga higher concentration than that of the drift region; (t) a collectorregion having the second conductivity type, arranged on the second mainsurface side of the field stop region in almost the entire region of thesilicon type semiconductor substrate; (v) an aluminum doped regionarranged on the second main surface side of the collector region inalmost the entire region of the silicon type semiconductor substrate,and having a higher concentration than that of the collector region; and(w) a metal collector electrode arranged in almost the entire region ofthe second main surface of the silicon type semiconductor substrate,wherein a portion of the metal collector electrode in contact with thealuminum doped region is a back surface metal film including aluminum asa main component.
 12. A method for manufacturing a narrow active cell IEtype trench gate IGBT, the IGBT, comprising: (a) a silicon typesemiconductor wafer having a first main surface and a second mainsurface; (b) an IGBT cell region arranged on the first main surface sideof the silicon type semiconductor wafer; (c) a drift region having afirst conductivity type arranged from the inside to the first mainsurface in almost the entire region of the silicon type semiconductorwafer; (d) a body region having a second conductivity type, arranged inthe surface region on the first main surface side of the silicon typesemiconductor wafer, and in almost the entire surface of the IGBT cellregion; (e) a plurality of linear active cell regions and a plurality oflinear inactive cell regions arranged in the IGBT cell region; (f) aplurality of active sections and a plurality of inactive sectionsalternately arrayed along the longitudinal direction of the each linearactive cell region; (g) a trench arranged in the first main surface ofthe silicon type semiconductor wafer, and at the boundary part betweenthe each linear active cell region and the each linear inactive cellregion; (h) a gate electrode arranged in the trench via an insulationfilm; (i) an emitter region having the first conductivity type arrangedin the surface region of the body region, and over almost the entireregion of the each active section; (j) a body contact region having thesecond conductivity type, arranged in the surface region of the bodyregion, and in the each inactive section; (k) a second conductivity typefloating region arranged in the surface region on the first main surfaceside of the silicon type semiconductor wafer, and in almost the entireregion of the each linear inactive cell region, in such a manner as toextend to the bottom ends of the trenches on the opposite sides thereof,and having a larger depth than that of the body region; and (m) a metalemitter electrode arranged over the first main surface of the silicontype semiconductor wafer, and electrically coupled to the emitter regionand the body contact region, the method comprising the steps of: (x1)introducing second conductivity type impurities for forming the secondconductivity type floating region in the first main surface of thesilicon type semiconductor wafer; (x2) after the step (x1), forming thetrench; (x3) after the step (x2), carrying out drive-in diffusion withrespect to the impurities introduced in the step (x1); (x4) after thestep (x3), forming the gate electrode; and (x5) after the step (x4),introducing second conductivity type impurities for forming the bodyregion.
 13. The method for manufacturing a narrow active cell IE typetrench gate IGBT according to claim 12, further comprising a step of:(x6) before the step (x1), introducing first conductivity typeimpurities for forming a hole barrier region into the first main surfaceof the silicon type semiconductor wafer.
 14. The method formanufacturing a narrow active cell IE type trench gate IGBT according toclaim 13, wherein the step (x1) is also used for introducing secondconductivity type impurities for forming a floating field ring arrangedin the peripheral outside of the IGBT cell region.
 15. The method formanufacturing a narrow active cell IE type trench gate IGBT according toclaim 14, further comprising a step of: (x7) after the step (x5),introducing first conductivity type impurities for forming the emitterregion.
 16. The method for manufacturing a narrow active cell IE typetrench gate IGBT according to claim 15, further comprising a step of:(x8) after the step (x7), introducing second conductivity typeimpurities for forming the body contact region.